ASIC and FPGA verification : a guide to component modeling /

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Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...

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Bibliographic Details
Call Number:Libro Electrónico
Main Author: Munden, Richard
Format: Electronic eBook
Language:Inglés
Published: San Francisco, Calif. : Morgan Kaufmann, ©2005.
Series:Morgan Kaufmann series in systems on silicon.
Subjects:
Application-specific integrated circuits.
Field programmable gate arrays.
Circuits intégrés à la demande.
Réseaux logiques programmables par l'utilisateur.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > VLSI & ULSI.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Logic.
COMPUTERS > Logic Design.
Application specific integrated circuits.
Field programmable gate arrays
Application-specific integrated circuits
Online Access:Texto completo (Requiere registro previo con correo institucional)
Table of Contents:
  • 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models.

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