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ASIC and FPGA verification : a guide to component modeling /
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...
| Clasificación: | Libro Electrónico |
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| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
San Francisco, Calif. :
Morgan Kaufmann,
©2005.
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| Colección: | Morgan Kaufmann series in systems on silicon.
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| Temas: | |
| Acceso en línea: | Texto completo (Requiere registro previo con correo institucional) |