Formal verification : an essential toolkit for modern VLSI design /

Afficher d'autres versions (3)

Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents th...

Description complète

Détails bibliographiques
Cote:Libro Electrónico
Auteur principal: Seligman, Erik
Autres auteurs: Schubert, Tom, Kumar, M. V. Achutha Kiran
Format: Électronique eBook
Langue:Inglés
Publié: Amsterdam : Elsevier Science, 2015.
Sujets:
Electronic circuits > Testing.
Integrated circuits > Very large scale integration > Design and construction.
Verilog (Computer hardware description language)
Verilog (Langage de description de mat�eriel informatique)
TECHNOLOGY & ENGINEERING > Mechanical.
Electronic circuits > Testing
Integrated circuits > Very large scale integration > Design and construction
Accès en ligne:Texto completo

Internet

Texto completo

Items no disponibles

Informations d'exemplaires de

Documents similaires