Digital circuit testing : a guide to DFT and other techniques /

"Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of el...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Wang, Francis C.
Formato: Electrónico eBook
Idioma:Inglés
Publicado: San Diego : Academic Press, �1991.
Temas:
Digital integrated circuits > Testing.
Circuits int�egr�es num�eriques > Essais.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > General.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Integrated.
Digitalschaltung
Testen
Circuits int�egr�es num�eriques.
Test circuit int�egr�e.
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Front Cover; Digital Circuit Testing: A Guide to DFT and Other Techniques; Copyright Page; Table of Contents; Preface; Chapter 1. Introduction; 1.1 Digital Circuits and Systems; 1.2 Fault Models Used in Digital Circuits Testing; 1.3 Fault Coverage Requirements; 1.4 The Design and Test Process; 1.5 Review of ATVG: D-Algorithm; 1.6 Review of ATVG: PODEM Algorithm; References; Chapter 2. A Test Generation Method Using Testability Results; 2.1 An Overview; 2.2 Background in Test Counting; 2.3 Sensitivity Analysis at a Fanout Node; 2.4 Local Enumeration Technique; 2.5 The Test Generation Process.
  • 2.6 SummaryReferences; Chapter 3. Sequential Circuit ATVG and DFT; 3.1 Introduction; 3.2 The Extended Backtrace Algorithm; 3.3 The BACK Algorithm; 3.4 A Simulation-Based Method: CONTEST; 3.5 DFT for Sequential Circuits; 3.6 Scan-Path Design Techniques; 3.7 Summary; References; Chapter 4. PLD Design for Test; 4.1 Introduction; 4.2 Why PLDs Should Be Tested; 4.3 What Needs To Be Tested?; 4.4 Effect of Device Types on Testability; 4.5 JEDEC Standard Format; 4.6 DFT Considerations for PLDs; 4.7 Features Important for ATVG; References; Chapter 5. Built-in Self Test and Boundary Scan Techniques.
  • 5.1 BIST Overview5.2 Test Generation in BIST; 5.3 Test Data Compression in BIST; 5.4 The BILBO Registers; 5.5 Subcircuit Partitioning and Diagnostics; 5.6 BIST Feature Summary; 5.7 Boundary Scan Overview; 5.8 Boundary Scan Applications; 5.9 Boundary Scan Implementation Considerations; References; Chapter 6. ATE and the Testing Process; 6.1 The Types of IC Testing; 6.2 Modern Semiconductor Testers; 6.3 Board-Level Simulation and Testing; 6.4 In-Cireuit Testers; 6.5 Functional Board Testers; 6.6 Linking Design and Test; References; Chapter 7. Special Testing Topics and Conclusions.
  • 7.1 Mixed Signal Testing and Simulation7.2 Microprocessor Testing and Simulation; 7.3 Conclusions; References; Index.

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