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Digital circuit testing : a guide to DFT and other techniques /
"Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of el...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
San Diego :
Academic Press,
�1991.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a2200000Ia 4500 | ||
|---|---|---|---|
| 001 | SCIDIR_ocn842936541 | ||
| 003 | OCoLC | ||
| 005 | 20231117044809.0 | ||
| 006 | m o d | ||
| 007 | cr cnu---unuuu | ||
| 008 | 130514s1991 caua ob 001 0 eng d | ||
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| 019 | |a 819749123 |a 850149191 | ||
| 020 | |a 9780080504346 |q (electronic bk.) | ||
| 020 | |a 0080504345 |q (electronic bk.) | ||
| 020 | |z 9780127345802 |q (cloth) | ||
| 020 | |z 0127345809 |q (cloth) | ||
| 035 | |a (OCoLC)842936541 |z (OCoLC)819749123 |z (OCoLC)850149191 | ||
| 050 | 4 | |a TK7874 |b .W363 1991eb | |
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| 082 | 0 | 4 | |a 621.381/5 |2 22 |
| 084 | |a ELT 468f |2 stub | ||
| 100 | 1 | |a Wang, Francis C. | |
| 245 | 1 | 0 | |a Digital circuit testing : |b a guide to DFT and other techniques / |c Francis C. Wang. |
| 260 | |a San Diego : |b Academic Press, |c �1991. | ||
| 300 | |a 1 online resource (xi, 233 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 504 | |a Includes bibliographical references and index. | ||
| 520 | |a "Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of electronic equipment and a great deal of emphasis is being placed on the development of these methods. Some of the techniques now becoming popular include design for testability (DFT), built-in self-test (BIST), and automatic test vector generation (ATVG). This book will provide a practical introduction to these and other testing techniques. For each technique introduced, the author provides real-world examples so the reader can achieve a working knowledge of how to choose and apply these increasingly important testing methods"--Provided by publisher. | ||
| 588 | 0 | |a Print version record. | |
| 505 | 0 | |a Front Cover; Digital Circuit Testing: A Guide to DFT and Other Techniques; Copyright Page; Table of Contents; Preface; Chapter 1. Introduction; 1.1 Digital Circuits and Systems; 1.2 Fault Models Used in Digital Circuits Testing; 1.3 Fault Coverage Requirements; 1.4 The Design and Test Process; 1.5 Review of ATVG: D-Algorithm; 1.6 Review of ATVG: PODEM Algorithm; References; Chapter 2. A Test Generation Method Using Testability Results; 2.1 An Overview; 2.2 Background in Test Counting; 2.3 Sensitivity Analysis at a Fanout Node; 2.4 Local Enumeration Technique; 2.5 The Test Generation Process. | |
| 505 | 8 | |a 2.6 SummaryReferences; Chapter 3. Sequential Circuit ATVG and DFT; 3.1 Introduction; 3.2 The Extended Backtrace Algorithm; 3.3 The BACK Algorithm; 3.4 A Simulation-Based Method: CONTEST; 3.5 DFT for Sequential Circuits; 3.6 Scan-Path Design Techniques; 3.7 Summary; References; Chapter 4. PLD Design for Test; 4.1 Introduction; 4.2 Why PLDs Should Be Tested; 4.3 What Needs To Be Tested?; 4.4 Effect of Device Types on Testability; 4.5 JEDEC Standard Format; 4.6 DFT Considerations for PLDs; 4.7 Features Important for ATVG; References; Chapter 5. Built-in Self Test and Boundary Scan Techniques. | |
| 505 | 8 | |a 5.1 BIST Overview5.2 Test Generation in BIST; 5.3 Test Data Compression in BIST; 5.4 The BILBO Registers; 5.5 Subcircuit Partitioning and Diagnostics; 5.6 BIST Feature Summary; 5.7 Boundary Scan Overview; 5.8 Boundary Scan Applications; 5.9 Boundary Scan Implementation Considerations; References; Chapter 6. ATE and the Testing Process; 6.1 The Types of IC Testing; 6.2 Modern Semiconductor Testers; 6.3 Board-Level Simulation and Testing; 6.4 In-Cireuit Testers; 6.5 Functional Board Testers; 6.6 Linking Design and Test; References; Chapter 7. Special Testing Topics and Conclusions. | |
| 505 | 8 | |a 7.1 Mixed Signal Testing and Simulation7.2 Microprocessor Testing and Simulation; 7.3 Conclusions; References; Index. | |
| 650 | 0 | |a Digital integrated circuits |x Testing. | |
| 650 | 6 | |a Circuits int�egr�es num�eriques |0 (CaQQLa)201-0069099 |x Essais. |0 (CaQQLa)201-0375087 | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x General. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Integrated. |2 bisacsh | |
| 650 | 7 | |a Digital integrated circuits |x Testing. |2 fast |0 (OCoLC)fst00893702 | |
| 650 | 7 | |a Digitalschaltung |2 gnd |0 (DE-588)4012295-5 | |
| 650 | 7 | |a Testen |2 gnd |0 (DE-588)4367264-4 | |
| 650 | 7 | |a Circuits int�egr�es num�eriques. |2 ram | |
| 650 | 7 | |a Test circuit int�egr�e. |2 ram | |
| 776 | 0 | 8 | |i Print version: |a Wang, Francis C. |t Digital circuit testing. |d San Diego : Academic Press, �1991 |z 0127345809 |w (DLC) 90029033 |w (OCoLC)22984341 |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9780127345802 |z Texto completo |