Skew-tolerant circuit design /

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As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of cl...

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Bibliographic Details
Call Number:Libro Electrónico
Main Author: Harris, David (David Lewis)
Format: Electronic eBook
Language:Inglés
Published: San Francisco : Morgan Kaufmann Publishers, ©2001.
Series:Morgan Kaufmann series in computer architecture and design.
Subjects:
Timing circuits > Design and construction.
Integrated circuits > Very large scale integration > Design and construction.
Synchronization.
Synchronisation.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Integrated.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > General.
Integrated circuits > Very large scale integration > Design and construction
Synchronization
Timing circuits > Design and construction
Online Access:Texto completo (Requiere registro previo con correo institucional)

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