Wafer-level testing and test during burn-in for integrated circuits /

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Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This...

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Bibliographic Details
Call Number:Libro Electrónico
Main Authors: Bahukudumbi, Sudarshan (Author), Chakrabarty, Krishnendu (Author)
Format: Electronic eBook
Language:Inglés
Published: Boston : Artech House, 2010.
Series:Artech House integrated microsystems series.
Subjects:
Integrated circuits > Testing.
Integrated circuits > Wafer-scale integration.
Semiconductors > Testing.
Circuits intégrés > Intégration sur la plaquette.
Semi-conducteurs > Essais.
TECHNOLOGY & ENGINEERING > Electronics > Microelectronics.
TECHNOLOGY & ENGINEERING > Electronics > Digital.
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