Loading…
ASIC and FPGA verification : a guide to component modeling /
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...
| Call Number: | Libro Electrónico |
|---|---|
| Main Author: | |
| Format: | Electronic eBook |
| Language: | Inglés |
| Published: |
San Francisco, Calif. :
Morgan Kaufmann,
©2005.
|
| Series: | Morgan Kaufmann series in systems on silicon.
|
| Subjects: | |
| Online Access: | Texto completo Texto completo |