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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test /
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays...
| Call Number: | Libro Electrónico |
|---|---|
| Main Authors: | , |
| Corporate Author: | |
| Format: | Electronic eBook |
| Language: | Inglés |
| Published: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2008.
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| Edition: | 1st ed. 2008. |
| Series: | Frontiers in Electronic Testing ;
40 |
| Subjects: | |
| Online Access: | Texto Completo |