Chargement en cours…
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies Process-Aware SRAM Design and Test /
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays...
| Cote: | Libro Electrónico |
|---|---|
| Auteurs principaux: | , |
| Collectivité auteur: | |
| Format: | Électronique eBook |
| Langue: | Inglés |
| Publié: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2008.
|
| Édition: | 1st ed. 2008. |
| Collection: | Frontiers in Electronic Testing ;
40 |
| Sujets: | |
| Accès en ligne: | Texto Completo |