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Testing for small-delay defects in nanoscale CMOS integrated circuits /

Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality is...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Otros Autores: Goel, Sandeep K. (Editor ), Chakrabarty, Krishnendu (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Boca Raton : CRC Press, Taylor & Francis Group, [2014]
Colección:Devices, circuits, and systems.
Temas:
Acceso en línea:Texto completo (Requiere registro previo con correo institucional)

MARC

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245 0 0 |a Testing for small-delay defects in nanoscale CMOS integrated circuits /  |c edited by Sandeep K. Goel, Krishnendu Chakrabarty. 
264 1 |a Boca Raton :  |b CRC Press, Taylor & Francis Group,  |c [2014] 
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505 0 |a Section 1. Timing-aware ATPG -- section 2. Faster-than-at-speed -- section 3. Alternative methods -- section 4. SDD metrics. 
520 |a Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay. 
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700 1 |a Goel, Sandeep K.,  |e editor. 
700 1 |a Chakrabarty, Krishnendu,  |e editor. 
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