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|a Testing for small-delay defects in nanoscale CMOS integrated circuits /
|c edited by Sandeep K. Goel, Krishnendu Chakrabarty.
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|b CRC Press, Taylor & Francis Group,
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|a Section 1. Timing-aware ATPG -- section 2. Faster-than-at-speed -- section 3. Alternative methods -- section 4. SDD metrics.
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|a Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay.
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|d Boca Raton : CRC Press, 2014
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