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Wafer-level testing and test during burn-in for integrated circuits /
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Boston :
Artech House,
2010.
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| Colección: | Artech House integrated microsystems series.
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| Temas: | |
| Acceso en línea: | Texto completo |