Leakage Current and Defect Characterization of Short Channel MOSFETs.

Annotation

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Roll, Guntrade
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Berlin : Logos Verlag Berlin, 2012.
Colección:Research at NaMLab Ser.
Temas:
Metal oxide semiconductor field-effect transistors.
Transistors MOSFET.
Metal oxide semiconductor field-effect transistors
Acceso en línea:Texto completo

MARC

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100 1 |a Roll, Guntrade. 
245 1 0 |a Leakage Current and Defect Characterization of Short Channel MOSFETs. 
260 |a Berlin :  |b Logos Verlag Berlin,  |c 2012. 
300 |a 1 online resource (242 pages) 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
490 1 |a Research at NaMLab Ser. ;  |v v. 2 
588 0 |a Print version record. 
505 0 |a Intro; 1 Introduction; 2 Fundamentals of Leakage Currents in MOSFET Devices; 2.1 Leakage through Gate Oxide; 2.1.1 Thermally Activated Gate Leakage; 2.1.2 Tunneling Leakage Through the Gate Dielectric; 2.2 Subthreshold Leakage from Source to Drain; 2.3 Leakage from Silicon Space Charge Regions to Transistor Bulk; 2.3.1 Leakage Current Mechanisms; 2.3.2 Perimeter Leakage from Source/Drain to Bulk; 2.3.3 Generation Leakage from Channel Region to Bulk; 3 Methodology; 3.1 Current Voltage Measurement; 3.1.1 Basic Current Voltage Characteristics; 3.1.2 Separation of Leakage Pathâ#x80;#x99;s. 
505 8 |a 3.1.3 Gated Diode Measurement3.2 Capacitance Voltage Measurement; 3.3 Charge Pumping Measurement; 3.4 Simulation; 3.4.1 Spice Simulation; 3.4.2 TCAD Simulation; 4 Impact of Implant Variations on PFET Leakage Current; 4.1 Process Flow; 4.2 TCAD Simulation of the Process; 4.3 Interface Traps; 4.4 Electrical Measurement and Simulation of Leakage Current; 4.4.1 Source/Drain Leakage; 4.4.2 Source/Drain Extension Leakage; 4.4.3 Generation Leakage from Channel Region to Bulk; 4.4.4 Gate Induced Drain Leakage; 4.4.5 Verification of the Defect Model: Gated Diode Measurement; 4.4.6 Gate Leakage. 
505 8 |a 4.4.7 Subthreshold Leakage4.4.8 Conclusion; 4.5 Carbon Implantation into Junction Extension; 4.5.1 Description of Experiment; 4.5.2 Electrical Characterization of Transistor Performance; 4.5.3 Interface Traps; 4.5.4 Carbon Dose Dependent Leakage Current; 4.5.5 Conclusion; 4.6 Arsenic and Phosphorus Implantation for Threshold Voltage Control; 4.6.1 Description of Experiment; 4.6.2 Electrical Characterization of Transistor Performance; 4.6.3 Leakage Current Dependent on Halo- and Vth Implant; 4.6.4 Conclusion; 5 Impact of High-k Process Adjustment on Transistor Leakage Current. 
505 8 |a 5.1 High-k Process Flow5.2 TCAD Simulation of the Process; 5.3 Interface Traps; 5.4 Electrical Measurement and Simulation of Leakage Current; 5.4.1 Source/Drain Leakage; 5.4.2 Source/Drain Extension Leakage; 5.4.3 Generation Leakage from Channel Region to Bulk; 5.4.4 Gate Induced Drain Leakage; 5.4.5 Gate Leakage; 5.4.6 Subthreshold Leakage; 5.4.7 Conclusion; 5.5 Comparison of Silicon Oxide and Silicon Nitride Extension Spacer; 5.5.1 Description of Experiment; 5.5.2 Electrical Characterization of Transistor Performance; 5.5.3 Leakage Current Dependence on the Spacer Dielectric. 
505 8 |a 5.5.4 Conclusion5.6 Germanium Implantation during Gate Patterning; 5.6.1 Description of Experiment; 5.6.2 Electrical Characterization of Transistor Performance; 5.6.3 Leakage Current Dependence on the Gate Patterning Process; 5.6.4 Conclusion; 6 Summary and Outlook; 6.1 Leakage Currents and Defect Distribution; 6.2 Carbon in the Junction Extension; 6.3 Vth- and Halo Implant; 6.4 Silicon Oxynitride vs. Hafnium Silicon Oxide Gate Dielectric; 6.4.1 Silicon Oxide vs. Silicon Nitride Extension Spacer; 6.4.2 Germanium Implantation for Gate Patterning; 6.5 Outlook; 7 Bibliography. 
500 |a 8 Personal Bibliography. 
520 8 |a Annotation  |b The continuous improvement in semiconductor technology requires field effect transistor scaling while maintaining acceptable leakage currents. This study analyzes the effect of scaling on the leakage current and defect distribution in peripheral DRAM transistors. The influence of important process changes, such as the high-k gate patterning and encapsulation as well as carbon co-implants in the source/drain junction are investigated by advanced electrical measurements and TCAD simulation. A complete model for the trap assisted leakage currents in the silicon bulk of the transistors is presented. 
590 |a ProQuest Ebook Central  |b Ebook Central Academic Complete 
650 0 |a Metal oxide semiconductor field-effect transistors. 
650 6 |a Transistors MOSFET. 
650 7 |a Metal oxide semiconductor field-effect transistors  |2 fast 
776 0 8 |i Print version:  |a Roll, Guntrade.  |t Leakage Current and Defect Characterization of Short Channel MOSFETs.  |d Berlin : Logos Verlag Berlin, ©2012  |z 9783832532611 
830 0 |a Research at NaMLab Ser. 
856 4 0 |u https://ebookcentral.uam.elogim.com/lib/uam-ebooks/detail.action?docID=5223913  |z Texto completo 
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938 |a YBP Library Services  |b YANK  |n 15139084 
994 |a 92  |b IZTAP 

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