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The Source/Drain Engineering of Nanoscale Germanium-based MOS Devices

This book mainly focuses on reducing the high parasitic resistance in the source/drain of germanium nMOSFET. With adopting of the Implantation After Germanide (IAG) technique, P and Sb co-implantation technique and Multiple Implantation and Multiple Annealing (MIMA) technique, the electron Schottky...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Li, Zhiqiang (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2016.
Edición:1st ed. 2016.
Colección:Springer Theses, Recognizing Outstanding Ph.D. Research,
Temas:
Acceso en línea:Texto Completo

MARC

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245 1 4 |a The Source/Drain Engineering of Nanoscale Germanium-based MOS Devices  |h [electronic resource] /  |c by Zhiqiang Li. 
250 |a 1st ed. 2016. 
264 1 |a Berlin, Heidelberg :  |b Springer Berlin Heidelberg :  |b Imprint: Springer,  |c 2016. 
300 |a XIV, 59 p. 52 illus., 49 illus. in color.  |b online resource. 
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490 1 |a Springer Theses, Recognizing Outstanding Ph.D. Research,  |x 2190-5061 
505 0 |a Introduction -- Ge-based Schottky barrier height modulation technology -- Metal germanide technology -- Contact resistance of Ge-based devices -- Conclusions. 
520 |a This book mainly focuses on reducing the high parasitic resistance in the source/drain of germanium nMOSFET. With adopting of the Implantation After Germanide (IAG) technique, P and Sb co-implantation technique and Multiple Implantation and Multiple Annealing (MIMA) technique, the electron Schottky barrier height of NiGe/Ge contact is modulated to 0.1eV, the thermal stability of NiGe is improved to 600℃ and the contact resistivity of metal/n-Ge contact is drastically reduced to 3.8×10−7Ω•cm2, respectively. Besides, a reduced source/drain parasitic resistance is demonstrated in the fabricated Ge nMOSFET. Readers will find useful information about the source/drain engineering technique for high-performance CMOS devices at future technology node. 
650 0 |a Semiconductors. 
650 0 |a Electronic circuits. 
650 0 |a Nanoscience. 
650 0 |a Condensed matter. 
650 1 4 |a Semiconductors. 
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650 2 4 |a Nanophysics. 
650 2 4 |a Condensed Matter Physics. 
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