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978-3-540-71431-6 |
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20230220143545.0 |
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cr nn 008mamaa |
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100301s2007 gw | s |||| 0|eng d |
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|a 9783540714316
|9 978-3-540-71431-6
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|a 10.1007/978-3-540-71431-6
|2 doi
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|a QA75.5-76.95
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|a UYA
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|a COM014000
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|a UYA
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|a 004.0151
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|a Reconfigurable Computing: Architectures, Tools and Applications
|h [electronic resource] :
|b Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007, Proceedings /
|c edited by Pedro C. Diniz, Eduardo Marques, Koen Bertels, Marcio Merino Fernandes, Joao M.P. Cardoso.
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| 250 |
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|a 1st ed. 2007.
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| 264 |
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|a Berlin, Heidelberg :
|b Springer Berlin Heidelberg :
|b Imprint: Springer,
|c 2007.
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| 300 |
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|a XIV, 394 p.
|b online resource.
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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|a online resource
|b cr
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|a text file
|b PDF
|2 rda
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|a Theoretical Computer Science and General Issues,
|x 2512-2029 ;
|v 4419
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| 505 |
0 |
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|a Architectures [Regular Papers] -- Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array -- A Configurable Multi-ported Register File Architecture for Soft Processor Cores -- MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture -- Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture -- Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs -- Systematic Customization of On-Chip Crossbar Interconnects -- Authentication of FPGA Bitstreams: Why and How -- Architectures [Short Papers] -- Design of a Reversible PLD Architecture -- Designing Heterogeneous FPGAs with Multiple SBs -- Mapping Techniques and Tools [Regular Papers] -- Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations -- Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware -- Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations -- A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions -- Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping -- The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining -- Hardware/Software Codesign for Embedded Implementation of Neural Networks -- Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues -- Mapping Techniques and Tools [Short Papers] -- About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations -- Arithmetic [Regular Papers] -- Switching Activity Models for Power Estimation in FPGA Multipliers -- Multiplication over on FPGA: A Survey -- A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm -- A Fast Finite Field Multiplier -- Applications [Regular Papers] -- Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval -- Image Processing Architecture for Local Features Computation -- A Compact Shader for FPGA-Based Volume Rendering Accelerators -- Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications -- FPGA-Accelerated Molecular Dynamics Simulations: An Overview -- Reconfigurable Hardware Acceleration of Canonical Graph Labelling -- Reconfigurable Computing for Accelerating Protein Folding Simulations -- Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits -- Applications [Short Papers] -- A Space Variant Mapping Architecture for Reliable Car Segmentation -- A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads -- Searching the Web with an FPGA Based Search Engine -- An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma -- Real Time Architectures for Moving-Objects Tracking -- Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller -- Multiple Sequence Alignment Using Reconfigurable Computing -- Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing.
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| 650 |
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|a Computer science.
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| 650 |
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|a Computers.
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| 650 |
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|a Microprocessors.
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| 650 |
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|a Computer architecture.
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| 650 |
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|a Computer networks .
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| 650 |
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|a Electronic digital computers-Evaluation.
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| 650 |
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|a Computer systems.
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| 650 |
1 |
4 |
|a Theory of Computation.
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| 650 |
2 |
4 |
|a Computer Hardware.
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| 650 |
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4 |
|a Processor Architectures.
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| 650 |
2 |
4 |
|a Computer Communication Networks.
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| 650 |
2 |
4 |
|a System Performance and Evaluation.
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| 650 |
2 |
4 |
|a Computer System Implementation.
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| 700 |
1 |
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|a Diniz, Pedro C.
|e editor.
|0 (orcid)0000-0003-3131-9367
|1 https://orcid.org/0000-0003-3131-9367
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
|
|a Marques, Eduardo.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
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|a Bertels, Koen.
|e editor.
|0 (orcid)0000-0001-9310-4885
|1 https://orcid.org/0000-0001-9310-4885
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
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|a Fernandes, Marcio Merino.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 700 |
1 |
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|a Cardoso, Joao M.P.
|e editor.
|4 edt
|4 http://id.loc.gov/vocabulary/relators/edt
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| 710 |
2 |
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|a SpringerLink (Online service)
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| 773 |
0 |
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|t Springer Nature eBook
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| 776 |
0 |
8 |
|i Printed edition:
|z 9783540836513
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| 776 |
0 |
8 |
|i Printed edition:
|z 9783540714309
|
| 830 |
|
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|a Theoretical Computer Science and General Issues,
|x 2512-2029 ;
|v 4419
|
| 856 |
4 |
0 |
|u https://doi.uam.elogim.com/10.1007/978-3-540-71431-6
|z Texto Completo
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| 912 |
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|a ZDB-2-SCS
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| 912 |
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|a ZDB-2-SXCS
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| 912 |
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|a ZDB-2-LNC
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| 950 |
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|a Computer Science (SpringerNature-11645)
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| 950 |
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|a Computer Science (R0) (SpringerNature-43710)
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