Cargando…
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits. It includes details of numerous "manufacturing-ready" GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level an...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2013.
|
| Edición: | 1st ed. 2013. |
| Temas: | |
| Acceso en línea: | Texto Completo |
Tabla de Contenidos:
- Regular vs Irregular TSV Placementfor 3D IC
- Steiner Routingfor 3D IC
- Buffer Insertion for 3D IC.- Low Power Clock Routing for 3D IC
- Power Delivery Network Design for 3D IC
- 3D Clock Routing for Pre-bond Testability
- TSV-to-TSV Coupling Analysis and Optimization
- TSV Current Crowding and Power Integrity
- Modeling of Atomic Concentration at the Wire-to-TSV Interface
- Multi-Objective Archetectural Floorplanning for 3D IC
- Thermal-aware Gate-level Placement for 3D IC
- 3D IC Cooling with Micro-Fluidic Channels
- Mechanical Reliability Analysis and Optimization for 3D IC
- Impact of Mechanical Stress on Timing Variation for 3D IC
- Chip/Package Co-Analysis of Mechanical Stress for 3D IC
- 3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations
- TSV Interfracial Crack Analysis and Optimization
- Ultra High Logic Designs Using Monolithic 3D Integration
- Impact of TSV Scaling on 3D IC Design Quality
- 3D-MAPS: 3DMassively Parallel Processor with Stacked Memory.