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Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits. It includes details of numerous "manufacturing-ready" GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level an...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2013.
|
| Edición: | 1st ed. 2013. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
| LEADER | 00000nam a22000005i 4500 | ||
|---|---|---|---|
| 001 | 978-1-4419-9542-1 | ||
| 003 | DE-He213 | ||
| 005 | 20220116003042.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 121204s2013 xxu| s |||| 0|eng d | ||
| 020 | |a 9781441995421 |9 978-1-4419-9542-1 | ||
| 024 | 7 | |a 10.1007/978-1-4419-9542-1 |2 doi | |
| 050 | 4 | |a TK7867-7867.5 | |
| 072 | 7 | |a TJFC |2 bicssc | |
| 072 | 7 | |a TEC008010 |2 bisacsh | |
| 072 | 7 | |a TJFC |2 thema | |
| 082 | 0 | 4 | |a 621.3815 |2 23 |
| 100 | 1 | |a Lim, Sung Kyu. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a Design for High Performance, Low Power, and Reliable 3D Integrated Circuits |h [electronic resource] / |c by Sung Kyu Lim. |
| 250 | |a 1st ed. 2013. | ||
| 264 | 1 | |a New York, NY : |b Springer New York : |b Imprint: Springer, |c 2013. | |
| 300 | |a XXVIII, 560 p. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file |b PDF |2 rda | ||
| 505 | 0 | |a Regular vs Irregular TSV Placementfor 3D IC -- Steiner Routingfor 3D IC -- Buffer Insertion for 3D IC.- Low Power Clock Routing for 3D IC -- Power Delivery Network Design for 3D IC -- 3D Clock Routing for Pre-bond Testability -- TSV-to-TSV Coupling Analysis and Optimization -- TSV Current Crowding and Power Integrity -- Modeling of Atomic Concentration at the Wire-to-TSV Interface -- Multi-Objective Archetectural Floorplanning for 3D IC -- Thermal-aware Gate-level Placement for 3D IC -- 3D IC Cooling with Micro-Fluidic Channels -- Mechanical Reliability Analysis and Optimization for 3D IC -- Impact of Mechanical Stress on Timing Variation for 3D IC -- Chip/Package Co-Analysis of Mechanical Stress for 3D IC -- 3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations -- TSV Interfracial Crack Analysis and Optimization -- Ultra High Logic Designs Using Monolithic 3D Integration -- Impact of TSV Scaling on 3D IC Design Quality -- 3D-MAPS: 3DMassively Parallel Processor with Stacked Memory. | |
| 520 | |a This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits. It includes details of numerous "manufacturing-ready" GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs. Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process. Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability. Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the electro-migration failure mechanisms in TSVs. Covers design-for-thermal-reliability in 3D ICs, including thermal-aware architectural floorplanning, gate-level placement techniques to alleviate thermal problems, and co-design and co-analysis of thermal, power delivery, and performance. Includes issues affecting design-for-mechanical-reliability in 3D ICs, such as the co-efficient of thermal expansion (CTE) mismatch between TSV and silicon substrate, device mobility and full-chip timing variations, and the impact of package elements. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Microtechnology. | |
| 650 | 0 | |a Microelectromechanical systems. | |
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Microsystems and MEMS. |
| 650 | 2 | 4 | |a Processor Architectures. |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9781441995414 |
| 776 | 0 | 8 | |i Printed edition: |z 9781441995438 |
| 776 | 0 | 8 | |i Printed edition: |z 9781489986962 |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-1-4419-9542-1 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||