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Error Control for Network-on-Chip Links
As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed t...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer New York : Imprint: Springer,
2012.
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| Edición: | 1st ed. 2012. |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 001 | 978-1-4419-9313-7 | ||
| 003 | DE-He213 | ||
| 005 | 20220119210932.0 | ||
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| 008 | 111007s2012 xxu| s |||| 0|eng d | ||
| 020 | |a 9781441993137 |9 978-1-4419-9313-7 | ||
| 024 | 7 | |a 10.1007/978-1-4419-9313-7 |2 doi | |
| 050 | 4 | |a TK7867-7867.5 | |
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| 100 | 1 | |a Fu, Bo. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a Error Control for Network-on-Chip Links |h [electronic resource] / |c by Bo Fu, Paul Ampadu. |
| 250 | |a 1st ed. 2012. | ||
| 264 | 1 | |a New York, NY : |b Springer New York : |b Imprint: Springer, |c 2012. | |
| 300 | |a XI, 151 p. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file |b PDF |2 rda | ||
| 505 | 0 | |a Introduction -- Solutions to Improve the Reliability of On-Chip Interconnects -- Networks-on-Chip (NoC) -- Error Control Coding for On-Chip Interconnects -- Energy Efficient Error Control Implementation -- Combining Error Control Codes with Crosstalk Reduction. | |
| 520 | |a As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links; Examines energy-efficient techniques for integrating multiple error control methods in on-chip interconnects; Introduces various design techniques to tradeoff the reliability and energy consumption of on-chip interconnects, including implementation of low link swing voltage and dynamic voltage scaling with error control codes, combination of Hamming product codes with type-II hybrid ARQ, and configurable error control codes implementation. . | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Computer-aided engineering. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design. |
| 700 | 1 | |a Ampadu, Paul. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9781489986337 |
| 776 | 0 | 8 | |i Printed edition: |z 9781441993120 |
| 776 | 0 | 8 | |i Printed edition: |z 9781441993144 |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-1-4419-9313-7 |z Texto Completo |
| 912 | |a ZDB-2-ENG | ||
| 912 | |a ZDB-2-SXE | ||
| 950 | |a Engineering (SpringerNature-11647) | ||
| 950 | |a Engineering (R0) (SpringerNature-43712) | ||