Designing Reliable and Efficient Networks on Chips

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another impor...

Descripción completa

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Murali, Srinivasan (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Dordrecht : Springer Netherlands : Imprint: Springer, 2009.
Edición:1st ed. 2009.
Colección:Lecture Notes in Electrical Engineering, 34
Temas:
Electronic circuits.
Electric power production.
Microprocessors.
Computer architecture.
Electronic Circuits and Systems.
Electrical Power Engineering.
Processor Architectures.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • NoC Design Methods
  • Designing Crossbar Based Systems
  • Netchip Tool Flow for NoC Design
  • Designing Standard Topologies
  • Designing Custom Topologies
  • Supporting Multiple Applications
  • Supporting Dynamic Application Patterns
  • NoC Reliability Mechanisms
  • Timing-Error Tolerant NoC Design
  • Analysis of NoC Error Recovery Schemes
  • Fault-Tolerant Route Generation
  • NoC Support for Reliable On-Chip Memories
  • Conclusions and Future Directions.

Ejemplares similares