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Designing Reliable and Efficient Networks on Chips
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another impor...
| Clasificación: | Libro Electrónico |
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| Autor principal: | |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2009.
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| Edición: | 1st ed. 2009. |
| Colección: | Lecture Notes in Electrical Engineering,
34 |
| Temas: | |
| Acceso en línea: | Texto Completo |