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Designing Reliable and Efficient Networks on Chips
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another impor...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Dordrecht :
Springer Netherlands : Imprint: Springer,
2009.
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| Edición: | 1st ed. 2009. |
| Colección: | Lecture Notes in Electrical Engineering,
34 |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 100 | 1 | |a Murali, Srinivasan. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a Designing Reliable and Efficient Networks on Chips |h [electronic resource] / |c by Srinivasan Murali. |
| 250 | |a 1st ed. 2009. | ||
| 264 | 1 | |a Dordrecht : |b Springer Netherlands : |b Imprint: Springer, |c 2009. | |
| 300 | |a X, 198 p. |b online resource. | ||
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| 490 | 1 | |a Lecture Notes in Electrical Engineering, |x 1876-1119 ; |v 34 | |
| 505 | 0 | |a NoC Design Methods -- Designing Crossbar Based Systems -- Netchip Tool Flow for NoC Design -- Designing Standard Topologies -- Designing Custom Topologies -- Supporting Multiple Applications -- Supporting Dynamic Application Patterns -- NoC Reliability Mechanisms -- Timing-Error Tolerant NoC Design -- Analysis of NoC Error Recovery Schemes -- Fault-Tolerant Route Generation -- NoC Support for Reliable On-Chip Memories -- Conclusions and Future Directions. | |
| 520 | |a Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design. | ||
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Electric power production. | |
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 1 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Electrical Power Engineering. |
| 650 | 2 | 4 | |a Processor Architectures. |
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| 830 | 0 | |a Lecture Notes in Electrical Engineering, |x 1876-1119 ; |v 34 | |
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