Designing Reliable and Efficient Networks on Chips

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another impor...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Murali, Srinivasan (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Dordrecht : Springer Netherlands : Imprint: Springer, 2009.
Edición:1st ed. 2009.
Colección:Lecture Notes in Electrical Engineering, 34
Temas:
Electronic circuits.
Electric power production.
Microprocessors.
Computer architecture.
Electronic Circuits and Systems.
Electrical Power Engineering.
Processor Architectures.
Acceso en línea:Texto Completo
Descripción
Sumario:Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
Descripción Física:X, 198 p. online resource.
ISBN:9781402097577
ISSN:1876-1119 ;

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