Nanometer Technology Designs High-Quality Delay Tests /

While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Ahmed, Nisar (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, NY : Springer US : Imprint: Springer, 2008.
Edición:1st ed. 2008.
Temas:
Electronic circuits.
Electronics.
Computer-aided engineering.
Nanotechnology.
Electrical engineering.
Electronic Circuits and Systems.
Electronics and Microelectronics, Instrumentation.
Computer-Aided Engineering (CAD, CAE) and Design.
Electrical and Electronic Engineering.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Introduction to path delay and transition delay fault models and test methods
  • At-speed test challenges for nanometer technology designs
  • Low-cost tester friendly design-for-test techniques
  • Improving test quality of current at-speed test methods
  • Functionally untestable fault list generation and avoidance
  • Timing-based ATPG for screening small delay faults
  • Faster-than-at-speed test considering IR-drop effects
  • IR-drop tolerant at-speed test pattern generation and application.

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