SAT-Based Scalable Formal Verification Solutions

Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and int...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Ganai, Malay (Autor), Gupta, Aarti (Autor)
Autor Corporativo: SpringerLink (Online service)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York, NY : Springer US : Imprint: Springer, 2007.
Edición:1st ed. 2007.
Colección:Integrated Circuits and Systems,
Temas:
Computer-aided engineering.
Electronic circuits.
Electrical engineering.
Computer-Aided Engineering (CAD, CAE) and Design.
Electronic Circuits and Systems.
Electrical and Electronic Engineering.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Design Verification Challenges
  • Design Verification Challenges
  • Background
  • Basic Infrastructure
  • Efficient Boolean Representation
  • Hybrid DPLL-Style SAT Solver
  • Falsification
  • SAT-Based Bounded Model Checking
  • Distributed SAT-Based BMC
  • Efficient Memory Modeling in BMC
  • BMC for Multi-Clock Systems
  • Proof Methods
  • Proof by Induction
  • Unbounded Model Checking
  • Abstraction/Refinement
  • Proof-Based Iterative Abstraction
  • Verification Procedure
  • SAT-Based Verification Framework
  • Synthesis for Verification.

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