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SAT-Based Scalable Formal Verification Solutions
Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and int...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2007.
|
| Edición: | 1st ed. 2007. |
| Colección: | Integrated Circuits and Systems,
|
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
| LEADER | 00000nam a22000005i 4500 | ||
|---|---|---|---|
| 001 | 978-0-387-69167-1 | ||
| 003 | DE-He213 | ||
| 005 | 20220116210557.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 100301s2007 xxu| s |||| 0|eng d | ||
| 020 | |a 9780387691671 |9 978-0-387-69167-1 | ||
| 024 | 7 | |a 10.1007/978-0-387-69167-1 |2 doi | |
| 050 | 4 | |a TA345-345.5 | |
| 072 | 7 | |a UGC |2 bicssc | |
| 072 | 7 | |a COM007000 |2 bisacsh | |
| 072 | 7 | |a UGC |2 thema | |
| 082 | 0 | 4 | |a 670.285 |2 23 |
| 100 | 1 | |a Ganai, Malay. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 245 | 1 | 0 | |a SAT-Based Scalable Formal Verification Solutions |h [electronic resource] / |c by Malay Ganai, Aarti Gupta. |
| 250 | |a 1st ed. 2007. | ||
| 264 | 1 | |a New York, NY : |b Springer US : |b Imprint: Springer, |c 2007. | |
| 300 | |a XXX, 330 p. 118 illus. |b online resource. | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 347 | |a text file |b PDF |2 rda | ||
| 490 | 1 | |a Integrated Circuits and Systems, |x 1558-9420 | |
| 505 | 0 | |a Design Verification Challenges -- Design Verification Challenges -- Background -- Basic Infrastructure -- Efficient Boolean Representation -- Hybrid DPLL-Style SAT Solver -- Falsification -- SAT-Based Bounded Model Checking -- Distributed SAT-Based BMC -- Efficient Memory Modeling in BMC -- BMC for Multi-Clock Systems -- Proof Methods -- Proof by Induction -- Unbounded Model Checking -- Abstraction/Refinement -- Proof-Based Iterative Abstraction -- Verification Procedure -- SAT-Based Verification Framework -- Synthesis for Verification. | |
| 520 | |a Functional verification has become an important aspect of the chip design process. Significant resources, both in industry and academia, are devoted to the design complexity and verification endeavors. SAT-Based Scalable Formal Verification Solutions discusses in detail several of the latest and interesting scalable SAT-based techniques including: Hybrid SAT Solver, Customized Bounded/Unbounded Model Checking, Distributed Model Checking, Proofs and Proof-based Abstraction Methods, Verification of Embedded Memory System & Multi-clock Systems, and Synthesis for Verification Paradigm. These techniques have been designed and implemented in a verification platform Verisol (formally called DiVer) and have been used successfully in industry. This book provides algorithmic details and engineering insights into devising scalable approaches for an effective realization. It also includes the authors' practical experiences and recommendations in verifying the large industry designs using VeriSol. The book is primarily written for researchers, scientists, and verification engineers who would like to gain an in-depth understanding of scalable SAT-based verification techniques. The book will also be of interest for CAD tool developers who would like to incorporate various SAT-based advanced techniques in their products. | ||
| 650 | 0 | |a Computer-aided engineering. | |
| 650 | 0 | |a Electronic circuits. | |
| 650 | 0 | |a Electrical engineering. | |
| 650 | 1 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design. |
| 650 | 2 | 4 | |a Electronic Circuits and Systems. |
| 650 | 2 | 4 | |a Electrical and Electronic Engineering. |
| 700 | 1 | |a Gupta, Aarti. |e author. |4 aut |4 http://id.loc.gov/vocabulary/relators/aut | |
| 710 | 2 | |a SpringerLink (Online service) | |
| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9780387517568 |
| 776 | 0 | 8 | |i Printed edition: |z 9781441943415 |
| 776 | 0 | 8 | |i Printed edition: |z 9780387691664 |
| 830 | 0 | |a Integrated Circuits and Systems, |x 1558-9420 | |
| 856 | 4 | 0 | |u https://doi.uam.elogim.com/10.1007/978-0-387-69167-1 |z Texto Completo |
| 912 | |a ZDB-2-SCS | ||
| 912 | |a ZDB-2-SXCS | ||
| 950 | |a Computer Science (SpringerNature-11645) | ||
| 950 | |a Computer Science (R0) (SpringerNature-43710) | ||