Functional Verification of Programmable Embedded Architectures A Top-Down Approach /
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many ex...
Clasificación: | Libro Electrónico |
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Autores principales: | , |
Autor Corporativo: | |
Formato: | Electrónico eBook |
Idioma: | Inglés |
Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2005.
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Edición: | 1st ed. 2005. |
Temas: | |
Acceso en línea: | Texto Completo |