Cargando…
VLSI test principles and architectures : design for testability /
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of indu...
| Clasificación: | Libro Electrónico |
|---|---|
| Otros Autores: | , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Amsterdam ; Boston :
Elsevier Morgan Kaufmann Publishers,
[2006]
|
| Colección: | Morgan Kaufmann series in systems on silicon.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a2200000 i 4500 | ||
|---|---|---|---|
| 001 | SCIDIR_ocn162573568 | ||
| 003 | OCoLC | ||
| 005 | 20231117014934.0 | ||
| 006 | m o d | ||
| 007 | cr cn||||||||| | ||
| 008 | 070806t20062006ne a ob 001 0 eng d | ||
| 040 | |a OPELS |b eng |e rda |e pn |c OPELS |d OCLCG |d OCLCQ |d N$T |d EBLCP |d MERUC |d E7B |d IDEBK |d UMI |d CEF |d NHM |d DEBSZ |d KNOVL |d OCLCO |d OCLCQ |d KNOVL |d WAU |d KNOVL |d OCLCF |d OCLCQ |d CUS |d OCLCQ |d OCLCO |d OCLCQ |d KNOVL |d YDXCP |d OCLCO |d OCLCQ |d OCLCO |d OCLCQ |d OCLCO |d COO |d OCLCO |d OCLCQ |d OCLCO |d AZK |d OCLCO |d AGLDB |d LVT |d TOA |d OCLCO |d MOR |d PIFAG |d ZCU |d OCLCQ |d JBG |d U3W |d BUF |d REB |d STF |d WRM |d D6H |d OCLCO |d OCLCQ |d VTS |d ICG |d INT |d VT2 |d AU@ |d OCLCO |d OCLCQ |d OCLCA |d REC |d OCLCO |d OCLCQ |d MERER |d LEAUB |d OCLCO |d OCLCQ |d DKC |d OCLCQ |d OCLCO |d OCLCQ |d K6U |d LUN |d OCLCQ |d OCLCO |d M8D |d OCLCO |d OCLCQ |d KSU |d OCL |d GZM |d OCLCQ |d OCLCO | ||
| 019 | |a 123441360 |a 154703466 |a 299750751 |a 434023516 |a 441775657 |a 648178245 |a 772045718 |a 856952279 |a 961513666 |a 962682390 |a 972045931 |a 988532552 |a 992014050 |a 1026460121 |a 1035711655 |a 1037790220 |a 1038699337 |a 1044324180 |a 1055404986 |a 1056398101 |a 1058118432 | ||
| 020 | |a 9780080474793 |q (electronic bk.) | ||
| 020 | |a 0080474799 |q (electronic bk.) | ||
| 020 | |z 9780123705976 |q (hbk.) | ||
| 020 | |z 0123705975 |q (hbk.) | ||
| 035 | |a (OCoLC)162573568 |z (OCoLC)123441360 |z (OCoLC)154703466 |z (OCoLC)299750751 |z (OCoLC)434023516 |z (OCoLC)441775657 |z (OCoLC)648178245 |z (OCoLC)772045718 |z (OCoLC)856952279 |z (OCoLC)961513666 |z (OCoLC)962682390 |z (OCoLC)972045931 |z (OCoLC)988532552 |z (OCoLC)992014050 |z (OCoLC)1026460121 |z (OCoLC)1035711655 |z (OCoLC)1037790220 |z (OCoLC)1038699337 |z (OCoLC)1044324180 |z (OCoLC)1055404986 |z (OCoLC)1056398101 |z (OCoLC)1058118432 | ||
| 050 | 4 | |a TK7874.75 |b .V587 2006eb | |
| 072 | 7 | |a TEC |x 008050 |2 bisacsh | |
| 072 | 7 | |a TEC |x 008030 |2 bisacsh | |
| 072 | 7 | |a COM |x 036000 |2 bisacsh | |
| 082 | 0 | 4 | |a 621.39/5 |2 22 |
| 084 | |a ZN 4030 |2 rvk | ||
| 084 | |a ZN 4950 |2 rvk | ||
| 084 | |a ZN 4952 |2 rvk | ||
| 245 | 0 | 0 | |a VLSI test principles and architectures : |b design for testability / |c edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen. |
| 264 | 1 | |a Amsterdam ; |a Boston : |b Elsevier Morgan Kaufmann Publishers, |c [2006] | |
| 264 | 4 | |c �2006 | |
| 300 | |a 1 online resource (xxx, 777 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 490 | 1 | |a The Morgan Kaufmann series in systems on silicon | |
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | |a Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang. | |
| 520 | |a This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. | ||
| 588 | 0 | |a Print version record. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Testing. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design and construction. | |
| 650 | 6 | |a Circuits int�egr�es �a tr�es grande �echelle |0 (CaQQLa)201-0117255 |x Essais. |0 (CaQQLa)201-0375087 | |
| 650 | 6 | |a Circuits int�egr�es �a tr�es grande �echelle |0 (CaQQLa)201-0117255 |x Conception et construction. |0 (CaQQLa)201-0377664 | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Circuits |x Logic. |2 bisacsh | |
| 650 | 7 | |a COMPUTERS |x Logic Design. |2 bisacsh | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Testing. |2 blmlsh | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Design. |2 blmlsh | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Design and construction |2 fast |0 (OCoLC)fst00975610 | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Design |2 fast |0 (OCoLC)fst00975608 | |
| 650 | 7 | |a Integrated circuits |x Very large scale integration |x Testing |2 fast |0 (OCoLC)fst00975618 | |
| 650 | 7 | |a Testen |2 gnd |0 (DE-588)4367264-4 | |
| 650 | 7 | |a VLSI |2 gnd |0 (DE-588)4117388-0 | |
| 650 | 7 | |a Circuitos integrados vlsi. |2 larpcal | |
| 700 | 1 | |a Wang, Laung-Terng, |e editor. | |
| 700 | 1 | |a Wu, Cheng-Wen, |c EE Ph. D., |e editor. | |
| 700 | 1 | |a Wen, Xiaoqing, |e editor. | |
| 776 | 0 | 8 | |i Print version: |t VLSI test principles and architectures. |d Amsterdam ; Boston : Elsevier Morgan Kaufmann Publishers, �2006 |z 0123705975 |z 9780123705976 |w (DLC) 2006006869 |w (OCoLC)64624834 |
| 830 | 0 | |a Morgan Kaufmann series in systems on silicon. | |
| 856 | 4 | 0 | |u https://sciencedirect.uam.elogim.com/science/book/9780123705976 |z Texto completo |