Algorithms and parallel VLSI architectures III : proceedings of the International Workshop, Algorithms and Parallel VLSI Architectures III, Leuven, Belgium, August 29-31, 1994 /

A comprehensive overview of the current evolution of research in algorithms, architectures and compilation for parallel systems is provided by this publication. The contributions focus specifically on domains where embedded systems are required, either oriented to application-specific or to programm...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor Corporativo: International Workshop on Algorithms and Parallel VLSI Architectures Louvain, Belgium
Otros Autores: Moonen, Marc S., 1963-, Catthoor, Francky
Formato: Electrónico Congresos, conferencias eBook
Idioma:Inglés
Publicado: Amsterdam ; New York : Elsevier, 1995.
Temas:
Parallel processing (Electronic computers) > Congresses.
Integrated circuits > Very large scale integration > Congresses.
Computer algorithms > Congresses.
Computer architecture > Congresses.
Parall�elisme (Informatique) > Congr�es.
Circuits int�egr�es �a tr�es grande �echelle > Congr�es.
Algorithmes > Congr�es.
Ordinateurs > Architecture > Congr�es.
REFERENCE > General.
Computer algorithms
Computer architecture
Integrated circuits > Very large scale integration
Parallel processing (Electronic computers)
Computers > Design
Congress
proceedings (reports)
Conference papers and proceedings
Conference papers and proceedings.
Actes de congr�es.
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Cover
  • TABLE OF CONTENTS
  • Introduction: algorithms and parallel VLSI architectures
  • PART 1: PARALLEL ALGORITHMS
  • Chapter 1. Subspace methods in system identification and source localization
  • Chapter 2. Pipelining the inverse updates RLS array by algorithmic engineering
  • Chapter 3. Hierarchical signal flow graph representation of the square-root covariance Kalman filter
  • Chapter 4. A systolic algorithm for block-regularized RLS identification
  • Chapter 5. Numerical analysis of a normalised RLS filter using a probability description of propagated data
  • Chapter 6. Adaptive approximate rotations for computing the symmetric EVD
  • Chapter 7. Parallel implementation of the double bracket matrix flow for eigenvalue- eigenvector computation and sorting
  • Chapter 8. Parallel block iterative solvers for heterogeneous computing environments
  • Chapter 9. Efficient VLSI architecture for residue to binary converter
  • PART 2: PARALLEL ARCHITECTURES
  • Chapter 10. A case study in algorithm-architecture codesign: hardware-accelerator for long integer arithmetic
  • Chapter 11. An optimisation methodology for mapping a diffusion algorithm for vision into a modular and flexible array architecture
  • Chapter 12. A scalable design for dictionary machines
  • Chapter 13. Systolic implementation of Smith and Waterman algorithm on a SIMD coprocessor
  • Chapter 14. Architecture and programming of parallel video signal processors
  • Chapter 15. A highly parallel single-chip video signal processor
  • Chapter 16. A memory efficient, programmable multi-processor architecture for real-time motion estimation type algorithms
  • Chapter 17. Instruction-level parallelism in asynchronous processor architectures
  • Chapter 18. High speed wood inspection using a parallel VLSI architecture
  • Chapter 19. CONVEX exemplar systems : scalable parallel processing
  • Chapter 20. Modelling the 2-D FCT on a multiprocessor system
  • Chapter 21. Parallel grep
  • PART 3: PARALLEL COMPILATION
  • Chapter 22. Compiling for massively parallel architectures: a perspective
  • Chapter 23. DIV, FLOOR, CEIL, MOD and STEP functions in nested loop programs and linearly bounded lattices
  • Chapter 24. Uniformisation techniques for reducible integral recurrence equations
  • Chapter 25. HOPP- A higher-order parallel programming model
  • Chapter 26. Design by transformation of synchronous descriptions
  • Chapter 27. Heuristics for evaluation of array expressions on state of the art massively parallel machines
  • Chapter 28. On factors limiting the generation of efficient compiler-parallelized programs
  • Chapter 29. From dependence analysis to communication code generation: the 'look forwards' model
  • Chapter 30. Mapping complex image processing algorithms onto heterogeneous multi- processors regarding architecture dependent performance parameters
  • Chapter 31. Optimal communication for a graph based DSP silicon compiler
  • Chapter 32. Resource-constrained software pipelining for high-level synthesis of DSP systems
  • Chapter 33. A portable testbed for evaluating different approaches to distributed logic simulation
  • Chapter 34. A simulator for optical parallel computer architectures.

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