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Verification techniques for system-level design /
This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as...
| Cote: | Libro Electrónico |
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| Auteur principal: | |
| Autres auteurs: | , |
| Format: | Électronique eBook |
| Langue: | Inglés |
| Publié: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers,
©2008.
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| Collection: | Morgan Kaufmann series in systems on silicon.
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| Sujets: | |
| Accès en ligne: | Texto completo (Requiere registro previo con correo institucional) |