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Hardware design verification : simulation and formal method-based approaches /
The Practical, Start-to-Finish Guide to Modern Digital Design Verification As digital logic designs grow larger and more complex, functional verification has become the number one bottleneck in the design process. Reducing verification time is crucial to project success, yet many practicing engineer...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Upper Saddle River, NJ :
Prentice Hall Professional Technical Reference,
©2005.
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| Colección: | Prentice Hall modern semiconductor design series.
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| Temas: | |
| Acceso en línea: | Texto completo (Requiere registro previo con correo institucional) |
MARC
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| 100 | 1 | |a Lam, William K. C., |d 1962- | |
| 245 | 1 | 0 | |a Hardware design verification : |b simulation and formal method-based approaches / |c William K. Lam. |
| 260 | |a Upper Saddle River, NJ : |b Prentice Hall Professional Technical Reference, |c ©2005. | ||
| 300 | |a 1 online resource (xxv, 585 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
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| 490 | 1 | |a Prentice Hall modern semiconductor design series | |
| 504 | |a Includes bibliographical references (pages 539-559) and index. | ||
| 505 | 0 | 0 | |g Ch. 1. |t invitation to design verification -- |g Ch. 2. |t Coding for verification -- |g Ch. 3. |t Simulator architectures and operations -- |g Ch. 4. |t Test bench organization and design -- |g Ch. 5. |t Test scenarios, assertions, and coverage -- |g Ch. 6. |t Debugging process and verification cycle -- |g Ch. 7. |t Formal verification preliminaries -- |g Ch. 8. |t Decision diagrams, equivalence checking, and symbolic simulation -- |g Ch. 9. |t Model checking and symbolic computation. |
| 520 | 8 | |a The Practical, Start-to-Finish Guide to Modern Digital Design Verification As digital logic designs grow larger and more complex, functional verification has become the number one bottleneck in the design process. Reducing verification time is crucial to project success, yet many practicing engineers have had little formal training in verification, and little exposure to the newest solutions. Hardware Design Verification systematically presents today's most valuable simulation-based and formal verification techniques, helping test and design engineers choose the best approach for each project, quickly gain confidence in their designs, and move into fabrication far more rapidly. College students will find that coverage of verification principles and common industry practices will help them prepare for jobs as future verification engineers. Author William K. Lam, one of the world's leading experts in design verification, is a recent winner of the Chairman's Award for Innovation, Sun Microsystems' most prestigious technical achievement award. Drawing on his wide-ranging experience, he introduces the foundational principles of verification, presents traditional techniques that have survived the test of time, and introduces emerging techniques for today's most challenging designs. Throughout, Lam emphasizes practical examples rather than mathematical proofs; wherever advanced math is essential, he explains it clearly and accessibly. Coverage includes Simulation-based versus formal verification: advantages, disadvantages, and tradeoffs Coding for verification: functional and timing correctness, syntactical and structure checks, simulation performance, and more Simulator architectures and operations, including event-driven, cycle-based, hybrid, and hardware-based simulators Testbench organization, design, and tools: creating a fast, efficient test environment Test scenarios and assertion: planning, test cases, test generators, commercial and Verilog assertions, and more Ensuring complete coverage, including code, parameters, functions, items, and cross-coverage The verification cycle: failure capture, scope reduction, bug tracking, simulation data dumping, isolation of underlying causes, revision control, regression, release mechanisms, and tape-out criteria An accessible introduction to the mathematics and algorithms of formal verification, from Boolean functions to state-machine equivalence and graph algorithms Decision diagrams, equivalence checking, and symbolic simulation Model checking and symbolic computation Simply put, Hardware Design Verification will help you improve and accelerate your entire verification process--from planning through tape-out--so you can get to market faster with higher quality designs. | |
| 546 | |a English. | ||
| 590 | |a O'Reilly |b O'Reilly Online Learning: Academic/Public Library Edition | ||
| 650 | 0 | |a Integrated circuits |x Verification. | |
| 650 | 6 | |a Circuits intégrés |x Vérification. | |
| 650 | 7 | |a Integrated circuits |x Verification. |2 fast |0 (OCoLC)fst00975600 | |
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| 830 | 0 | |a Prentice Hall modern semiconductor design series. | |
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