ReRAM-based machine learning /

Serving as a bridge between researchers in the computing domain and computing hardware designers, this book presents ReRAM techniques for distributed computing using IMC accelerators, ReRAM-based IMC architectures for machine learning (ML) and data-intensive applications, and strategies to map ML de...

Descripción completa

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Yu, Hao (Autor), Ni, Leibin (Autor), Pudukotai Dinakarrao, Sai Manoj (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: London : Institution of Engineering & Technology 2021
Colección:IET computing series ; 39
Temas:
Machine learning.
Nonvolatile random-access memory.
Apprentissage automatique.
Ordinateurs > Mémoires vives non volatiles.
Machine learning
Nonvolatile random-access memory
AI chips.
compressed sensing.
learning (artificial intelligence)
resistive RAM.
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Cover
  • Contents
  • Acronyms
  • Preface
  • About the authors
  • Part I. Introduction
  • 1 Introduction
  • 1.1 Introduction
  • 1.1.1 Memory wall and powerwall
  • 1.1.2 Semiconductor memory
  • 1.1.2.1 Memory technologies
  • 1.1.2.2 Nanoscale limitations
  • 1.1.3 Nonvolatile IMC architecture
  • 1.2 Challenges and contributions
  • 1.3 Book organization
  • 2 The need of in-memory computing
  • 2.1 Introduction
  • 2.2 Neuromorphic computing devices
  • 2.2.1 Resistive random-access memory
  • 2.2.2 Spin-transfer-torque magnetic random-access memory
  • 2.2.3 Phase change memory
  • 2.3 Characteristics of NVM devices for neuromorphic computing
  • 2.4 IMC architectures for machine learning
  • 2.4.1 Operating principles of IMC architectures
  • 2.4.1.1 In-macro operating schemes
  • 2.4.1.2 Architectures for operating schemes
  • 2.4.2 Analog and digitized fashion of IMC
  • 2.4.3 Analog IMC
  • 2.4.3.1 Analog MAC
  • 2.4.3.2 Cascading IMC macros
  • 2.4.3.3 Bitcell and array design of analog IMC
  • 2.4.3.4 Peripheral circuitry of analog IMC
  • 2.4.3.5 Challenges of analog IMC
  • 2.4.3.6 Trade-offs of analog IMC devices
  • 2.4.4 Digitized IMC
  • 2.4.5 Literature review of IMC
  • 2.4.5.1 DRAM-based IMCs
  • 2.4.5.2 NAND-Flash-based IMCs
  • 2.4.5.3 SRAM-based IMCs
  • 2.4.5.4 ReRAM-based IMCs
  • 2.4.5.5 STT-MRAM-based IMCs
  • 2.4.5.6 SOT-MRAM-based IMCs
  • 2.5 Analysis of IMC architectures
  • 3 The background of ReRAM devices
  • 3.1 ReRAM device and SPICE model
  • 3.1.1 Drift-type ReRAM device
  • 3.1.2 Diffusive-type ReRAM device
  • 3.2 ReRAM-crossbar structure
  • 3.2.1 Analog and digitized ReRAM crossbar
  • 3.2.1.1 Traditional analog ReRAM crossbar
  • 3.2.1.2 Digitalized ReRAM crossbar
  • 3.2.2 Connection of ReRAM crossbar
  • 3.2.2.1 Direct-connected ReRAM
  • 3.2.2.2 One-transistor-one-ReRAM
  • 3.2.2.3 One-selector-one-ReRAM
  • 3.3 ReRAM-based oscillator
  • 3.4 Write-in scheme for multibit ReRAM storage
  • 3.4.1 ReRAM data storage
  • 3.4.2 Multi-threshold resistance for data storage
  • 3.4.3 Write and read
  • 3.4.3.1 Write-in method
  • 3.4.3.2 Readout method
  • 3.4.4 Validation
  • 3.4.5 Encoding and 3-bit storage
  • 3.4.5.1 Exploration of the memristance range
  • 3.4.5.2 Uniform input encoding
  • 3.4.5.3 Nonuniform encoding
  • 3.5 Logic functional units with ReRAM
  • 3.5.1 OR gate
  • 3.5.2 AND gate
  • 3.6 ReRAM for logic operations
  • 3.6.1 Simulation settings
  • 3.6.2 ReRAM-based circuits
  • 3.6.2.1 Logic operations
  • 3.6.2.2 Readout circuit
  • 3.6.3 ReRAM as a computational unit-cum-memory
  • Part II. Machine learning accelerators
  • 4 The background of machine learning algorithms
  • 4.1 SVM-based machine learning
  • 4.2 Single-layer feedforward neural network-based machine learning
  • 4.2.1 Single-layer feedforward network
  • 4.2.1.1 Feature extraction
  • 4.2.1.2 Neural network-based learning
  • 4.2.1.3 Incremental LS solver-based learning
  • 4.2.2 L2-norm-gradient-based learning
  • 4.2.2.1 Multilayer neural network
  • 4.2.2.2 Direct-gradient-based L2-norm optimization

Ejemplares similares