Practical digital design : an introduction to VHDL /

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CHAPTER 7 SEQUENTIAL STATEMENTS -- Null Statement -- Wait Statement -- If Statement -- Case Statement -- Loop Statement -- Loop Control Statements -- Assertion and Report Statements -- Signal Assignment -- Variable Assignment -- Summary -- CHAPTER 8 THE PROCESS STATEMENT -- Process Review -- Combina...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Reidenbach, Bruce, 1960- (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: West Lafayette, IN : Purdue University Press, [2022]
Temas:
VHDL (Computer hardware description language)
VHDL (Langage de description de matériel informatique)
COMPUTERS / Computer Engineering
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Cover
  • PRACTICAL DIGITAL DESIGN
  • Title
  • Copyright
  • Dedication
  • TABLE OF CONTENTS
  • PREFACE
  • ACKNOWLEDGMENTS
  • ABOUT THE AUTHOR
  • CHAPTER 1 INTRODUCTION
  • Target Audience
  • A Brief History of Digital Design
  • The Need for a Hardware Description Language
  • A Brief Tour of a VHDL Model
  • CHAPTER 2 SIGNALS, TIME, AND THE SIMULATION CYCLE
  • Signals
  • Events
  • Drivers
  • Delta Time
  • The Simulation Cycle
  • CHAPTER 3 THE VHDL DESIGN ENVIRONMENT
  • Modeling Styles
  • Design Flow
  • Data Types
  • Type Definition
  • Vector Data Types
  • Operators and Precedence
  • Design Libraries
  • Predefined Packages
  • STANDARD Package
  • STD_LOGIC_1164 Package
  • NUMERIC_STD Package
  • TEXTIO Package
  • Type Conversion
  • Type Qualification
  • Attributes
  • VHDL Language Versions
  • Coding Style
  • Vertical Alignment
  • VHDL Identifier Naming Rules
  • Comments
  • CHAPTER 4 DECLARATIONS
  • Syntax Notation
  • Object Declaration Syntax
  • Custom Type Declarations
  • Integer Types
  • Floating Point Types
  • Enumerated Types
  • Array Types
  • Record Types
  • Physical Types
  • Access Types
  • Alias Declarations
  • CHAPTER 5 LIBRARIES AND DESIGN UNITS
  • Library Units
  • Entity Declaration
  • Ports
  • Generics
  • Architecture Declaration
  • Package Declaration
  • Package Body Declaration
  • Configuration Declaration
  • Design Units
  • Context Clause
  • Summary
  • CHAPTER 6 CONCURRENT STATEMENTS
  • Conditional Signal Assignment Statement
  • Selected Signal Assignment Statement
  • Waveform Specification
  • Delay Models
  • Generate Statement
  • Component Instantiation
  • Concurrent Assertion Statement
  • Component Declaration
  • Configuration Specification
  • Component Instantiation Statement
  • Direct Entity Instantiation
  • Block Statement
  • Process Statement
  • Behavioral Model
  • Synthesizable Model
  • Structural Model
  • Summary
  • Engine Management System
  • CHAPTER 10 SUBPROGRAMS
  • Functions
  • Return Statements
  • Examples
  • Overloading
  • Pure versus Impure Functions
  • Procedures
  • Return Statements
  • Parameter Passing Details
  • Signal Parameters
  • Concurrent Procedure Calls
  • Procedures as Functions
  • Summary
  • CHAPTER 11 SIMULATION AND TEST BENCHES
  • Simulation
  • Simulation Phases
  • Test Benches
  • Test Bench Control
  • Races
  • Input Drivers
  • Output Monitors
  • Test Bench Example
  • Test Bench Types
  • Directed Testing

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