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Practical digital design : an introduction to VHDL /
CHAPTER 7 SEQUENTIAL STATEMENTS -- Null Statement -- Wait Statement -- If Statement -- Case Statement -- Loop Statement -- Loop Control Statements -- Assertion and Report Statements -- Signal Assignment -- Variable Assignment -- Summary -- CHAPTER 8 THE PROCESS STATEMENT -- Process Review -- Combina...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
West Lafayette, IN :
Purdue University Press,
[2022]
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Reidenbach, Bruce, |d 1960- |e author. | |
| 245 | 1 | 0 | |a Practical digital design : |b an introduction to VHDL / |c Bruce Reidenbach. |
| 264 | 1 | |a West Lafayette, IN : |b Purdue University Press, |c [2022] | |
| 300 | |a 1 online resource | ||
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| 505 | 0 | |a Cover -- PRACTICAL DIGITAL DESIGN -- Title -- Copyright -- Dedication -- TABLE OF CONTENTS -- PREFACE -- ACKNOWLEDGMENTS -- ABOUT THE AUTHOR -- CHAPTER 1 INTRODUCTION -- Target Audience -- A Brief History of Digital Design -- The Need for a Hardware Description Language -- A Brief Tour of a VHDL Model -- CHAPTER 2 SIGNALS, TIME, AND THE SIMULATION CYCLE -- Signals -- Events -- Drivers -- Delta Time -- The Simulation Cycle -- CHAPTER 3 THE VHDL DESIGN ENVIRONMENT -- Modeling Styles -- Design Flow -- Data Types -- Type Definition -- Vector Data Types -- Operators and Precedence | |
| 505 | 8 | |a Design Libraries -- Predefined Packages -- STANDARD Package -- STD_LOGIC_1164 Package -- NUMERIC_STD Package -- TEXTIO Package -- Type Conversion -- Type Qualification -- Attributes -- VHDL Language Versions -- Coding Style -- Vertical Alignment -- VHDL Identifier Naming Rules -- Comments -- CHAPTER 4 DECLARATIONS -- Syntax Notation -- Object Declaration Syntax -- Custom Type Declarations -- Integer Types -- Floating Point Types -- Enumerated Types -- Array Types -- Record Types -- Physical Types -- Access Types -- Alias Declarations -- CHAPTER 5 LIBRARIES AND DESIGN UNITS -- Library Units | |
| 505 | 8 | |a Entity Declaration -- Ports -- Generics -- Architecture Declaration -- Package Declaration -- Package Body Declaration -- Configuration Declaration -- Design Units -- Context Clause -- Summary -- CHAPTER 6 CONCURRENT STATEMENTS -- Conditional Signal Assignment Statement -- Selected Signal Assignment Statement -- Waveform Specification -- Delay Models -- Generate Statement -- Component Instantiation -- Concurrent Assertion Statement -- Component Declaration -- Configuration Specification -- Component Instantiation Statement -- Direct Entity Instantiation -- Block Statement -- Process Statement | |
| 505 | 8 | |a Behavioral Model -- Synthesizable Model -- Structural Model -- Summary -- Engine Management System -- CHAPTER 10 SUBPROGRAMS -- Functions -- Return Statements -- Examples -- Overloading -- Pure versus Impure Functions -- Procedures -- Return Statements -- Parameter Passing Details -- Signal Parameters -- Concurrent Procedure Calls -- Procedures as Functions -- Summary -- CHAPTER 11 SIMULATION AND TEST BENCHES -- Simulation -- Simulation Phases -- Test Benches -- Test Bench Control -- Races -- Input Drivers -- Output Monitors -- Test Bench Example -- Test Bench Types -- Directed Testing | |
| 520 | |a CHAPTER 7 SEQUENTIAL STATEMENTS -- Null Statement -- Wait Statement -- If Statement -- Case Statement -- Loop Statement -- Loop Control Statements -- Assertion and Report Statements -- Signal Assignment -- Variable Assignment -- Summary -- CHAPTER 8 THE PROCESS STATEMENT -- Process Review -- Combinatorial Logic -- Level Sensitive Latches -- Clocked Logic -- Process Examples -- Register Files -- Shift Registers -- Adders -- Counters -- State Machines -- Memory Arrays -- Process Construction Guidelines -- Summary -- CHAPTER 9 MODELING CASE STUDIES -- Modeling Style -- Binary Adder. | ||
| 588 | 0 | |a Online resource; title from digital title page (viewed on June 08, 2022). | |
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| 650 | 0 | |a VHDL (Computer hardware description language) | |
| 650 | 6 | |a VHDL (Langage de description de matériel informatique) | |
| 650 | 7 | |a COMPUTERS / Computer Engineering |2 bisacsh | |
| 650 | 7 | |a VHDL (Computer hardware description language) |2 fast | |
| 776 | 0 | 8 | |i Print version: |a Reidenbach, Bruce, 1960- |t Practical Digital Design. |d West Lafayette, IN : Purdue University Press, ©2022 |
| 856 | 4 | 0 | |u https://jstor.uam.elogim.com/stable/10.2307/j.ctv224v1b6 |z Texto completo |
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