Wafer-level testing and test during burn-in for integrated circuits /

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Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Bahukudumbi, Sudarshan (Autor), Chakrabarty, Krishnendu (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Boston : Artech House, 2010.
Colección:Artech House integrated microsystems series.
Temas:
Integrated circuits > Testing.
Integrated circuits > Wafer-scale integration.
Semiconductors > Testing.
Circuits intégrés > Intégration sur la plaquette.
Semi-conducteurs > Essais.
TECHNOLOGY & ENGINEERING > Electronics > Microelectronics.
TECHNOLOGY & ENGINEERING > Electronics > Digital.
Acceso en línea:Texto completo
Tabla de Contenidos:
  • Wafer-Level Test and Burn-In: Industry Practices and Trends
  • Resource-Constrained Testing of Core-Based ScCs
  • Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs
  • Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs
  • Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering
  • Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation.

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