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Wafer-level testing and test during burn-in for integrated circuits /
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Boston :
Artech House,
2010.
|
| Colección: | Artech House integrated microsystems series.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Bahukudumbi, Sudarshan. |e author. |4 aut | |
| 245 | 1 | 0 | |a Wafer-level testing and test during burn-in for integrated circuits / |c Sudarshan Bahukudumbi, Krishnendu Chakrabarty. |
| 260 | |a Boston : |b Artech House, |c 2010. | ||
| 300 | |a 1 online resource (xv, 198 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
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| 490 | 1 | |a Artech House integrated microsystems series | |
| 504 | |a Includes bibliographical references and index. | ||
| 520 | |a Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions. | ||
| 505 | 0 | |a Wafer-Level Test and Burn-In: Industry Practices and Trends -- Resource-Constrained Testing of Core-Based ScCs -- Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs -- Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SoCs -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Ordering -- Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation. | |
| 588 | 0 | |a Print version record. | |
| 590 | |a eBooks on EBSCOhost |b EBSCO eBook Subscription Academic Collection - Worldwide | ||
| 650 | 0 | |a Integrated circuits |x Testing. | |
| 650 | 0 | |a Integrated circuits |x Wafer-scale integration. | |
| 650 | 0 | |a Semiconductors |x Testing. | |
| 650 | 6 | |a Circuits intégrés |x Intégration sur la plaquette. | |
| 650 | 6 | |a Semi-conducteurs |x Essais. | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Microelectronics. |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING |x Electronics |x Digital. |2 bisacsh | |
| 650 | 7 | |a Integrated circuits |x Testing. |2 fast |0 (OCoLC)fst00975593 | |
| 650 | 7 | |a Integrated circuits |x Wafer-scale integration. |2 fast |0 (OCoLC)fst00975620 | |
| 650 | 7 | |a Semiconductors |x Testing. |2 fast |0 (OCoLC)fst01112261 | |
| 700 | 1 | |a Chakrabarty, Krishnendu. |e author. |4 aut | |
| 776 | 0 | 8 | |i Print version: |a Bahukudumbi, Sudarshan. |t Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty. |d Boston : Artech House, 2010 |z 1596939893 |w (DLC) 2010455090 |w (OCoLC)449516460 |
| 830 | 0 | |a Artech House integrated microsystems series. | |
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