Cita APA (7a ed.)

Bahukudumbi, S., & Chakrabarty, K. (2010). Wafer-level testing and test during burn-in for integrated circuits. Artech House.

Cita Chicago Style (17a ed.)

Bahukudumbi, Sudarshan, y Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Boston: Artech House, 2010.

Cita MLA (8a ed.)

Bahukudumbi, Sudarshan, y Krishnendu Chakrabarty. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Artech House, 2010.