Verification techniques for system-level design /

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This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as...

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Bibliographic Details
Call Number:Libro Electrónico
Main Author: Fujita, Masahiro, 1956-
Other Authors: Ghosh, Indradeep, 1970-, Prasad, Mukul
Format: Electronic eBook
Language:Inglés
Published: Amsterdam ; Boston : Morgan Kaufmann Publishers, ©2008.
Series:Morgan Kaufmann series in systems on silicon.
Subjects:
Systems on a chip > Testing.
Integrated circuits > Verification.
Formal methods (Computer science)
Circuits intégrés > Vérification.
Méthodes formelles (Informatique)
TECHNOLOGY & ENGINEERING > Electronics > Circuits > Integrated.
TECHNOLOGY & ENGINEERING > Electronics > Circuits > General.
Integrated circuits > Verification
Online Access:Texto completo
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Search Result 1
Verification techniques for system-level design /
by Fujita, Masahiro, 1956-
Published 2008
Texto completo (Requiere registro previo con correo institucional)
Electronic eBook
Search Result 2
Verification Techniques for System-Level Design.
by Fujita, Masahiro
Published 2007
Texto completo
Electronic eBook
Search Result 3
Verification techniques for system-level design /
by Fujita, Masahiro, 1956-
Published 2008
Texto completo
Electronic eBook
Show all versions (4)

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