Digital systems design. Volume III, Latch-flip-flop circuits and characteristics of digital circuits /

Working as an engineer with advanced weapon systems for more than 25 years, it was crucial to understand the fundamentals of digital systems design development methods and combinational logic circuits. Whether as a technician or as an engineer, these fundamentals are the basics of engineering and ar...

Descripción completa

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor principal: Massengale, Larry (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: New York : Momentum Press, 2019.
Colección:Engineering technology collection.
Temas:
System design.
Logic circuits.
Digital electronics.
Conception de systèmes.
Circuits logiques.
Électronique numérique.
Logic circuits
Digital electronics
System design
Acceso en línea:Texto completo
Tabla de Contenidos:
  • 1. Latch and flip flop circuits
  • 1.1. Introduction
  • 1.2. Active low latch
  • NAND gate latch
  • 1.3. Active high latch
  • NOR gate latch
  • 1.4. Active low gated set-clear (S-C) latch
  • 1.5. Active low gated D latch
  • 1.6. Four-bit bistable latches
  • 1.6.1. SN74LS75
  • 1.6.2. SN74LS77
  • 1.7. D-type flip flop: positive edge triggered D-type flip flop
  • 1.7.1. Negative edge triggered D-type flip flop
  • 1.8. JK-type flip flop: positive edge triggered JK flip flop
  • 1.9. Master-slave JK-type flip flop
  • 1.10. Chapter 1 review questions
  • 1.11. Chapter 1 review answers
  • 2. Characteristics of digital circuits
  • 2.1. Introduction
  • 2.2. RC time constant
  • 2.2.1. Charging
  • 2.2.2. Discharging
  • 2.3. Electrical behavior of circuits
  • 2.3.1 Data sheets and specifications
  • 2.3.2. Logic levels and noise margins
  • 2.3.2.1. Logic level
  • 2.3.2.2. Noise margin
  • 2.3.3. Circuit behavior with circuit loads
  • 2.3.4. Fan-outs
  • 2.3.5. Effects of loading
  • 2.3.6. Unused inputs
  • 2.3.7. Current spikes and decoupling capacitors
  • 2.3.8. Destruction of CMOS devices
  • 2.4. Dynamic electrical behavior
  • 2.4.1. Gate delays and timing diagrams
  • 2.4.2. Transition time
  • 2.4.3. Propagation delay
  • 2.4.4. Power consumption
  • 2.5. Timing considerations
  • 2.5.1. Setup and hold times
  • 2.5.2. Maximum clocking frequency fMAX
  • 2.5.3. Clock pulse high and low times
  • 2.5.4. Asynchronous active pulse width
  • 2.5.5. Clock transition times
  • 2.6. Data storage and transfer
  • 2.6.1. Flip flops form registers
  • 2.6.2. Serial input serial output (SISO)
  • 2.6.3. Serial input parallel output (SIPO)
  • 2.6.4. Parallel input serial output (PISO)
  • 2.6.4.1. Shift mode
  • 2.6.5. Parallel input parallel output (PIPO)
  • 2.6.5.1. Bidirectional shift register
  • 2.6.5.2. Universal shift register
  • 2.7. Chapter 2 review
  • questions
  • 2.8. Chapter 2 review
  • answers

Ejemplares similares