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Vertical 3D Memory Technologies.
The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then p...
| Clasificación: | Libro Electrónico |
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| Autor principal: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Hoboken :
Wiley,
2014.
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| Temas: | |
| Acceso en línea: | Texto completo |
| Sumario: | The large scale integration and planar scaling of individual system chips is reaching an expensive limit. If individual chips now, and later terrabyte memory blocks, memory macros, and processing cores, can be tightly linked in optimally designed and processed small footprint vertical stacks, then performance can be increased, power reduced and cost contained. This book reviews for the electronics industry engineer, professional and student the critical areas of development for 3D vertical memory chips including: gate-all-around and junction-less nanowire memories, stacked thin film and dou. |
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| Notas: | 3.1 Overview of GAA Nanowire Memories. |
| Descripción Física: | 1 online resource (371 pages) |
| Bibliografía: | Includes bibliographical references and index. |
| ISBN: | 9781118760451 111876045X |