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Transient-induced latchup in CMOS integrated circuits /
"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the c...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor principal: | |
| Otros Autores: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
[Piscataway, NJ] : Singapore ; Hoboken, NJ :
IEEE Press ; John Wiley & Sons (Asia),
©2009.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
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| 100 | 1 | |a Ker, Ming-Dou. | |
| 245 | 1 | 0 | |a Transient-induced latchup in CMOS integrated circuits / |c Ming-Dou Ker and Sheng-Fu Hsu. |
| 260 | |a [Piscataway, NJ] : |b IEEE Press ; |a Singapore ; |a Hoboken, NJ : |b John Wiley & Sons (Asia), |c ©2009. | ||
| 300 | |a 1 online resource (xiii, 249 pages) : |b illustrations | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 504 | |a Includes bibliographical references and index. | ||
| 505 | 0 | 0 | |g 1. |t Introduction -- |g 2. |t Physical Mechanism of TLU under the System-Level ESD Test -- |g 3. |t Component-Level Measurement for TLU under System-Level ESD Considerations -- |g 4. |t TLU Dependency on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits -- |g 5. |t TLU in CMOS ICs in the Electrical Fast Transient Test -- |g 6. |t Methodology on Extracting Compact Layout Rules for Latchup Prevention -- |g 7. |t Special Layout Issues for Latchup Prevention -- |g 8. |t TLU Prevention in Power-Rail ESD Clamp Circuits -- |g 9. |t Summary -- |g Appendix A. |t Practical Application--Extractions of Latchup Design Rules in a 0.18-[mu]m 1.8 V/3.3V Silicided CMOS Process. |
| 520 | |a "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description. | ||
| 588 | 0 | |a Print version record. | |
| 590 | |a ProQuest Ebook Central |b Ebook Central Academic Complete | ||
| 650 | 0 | |a Metal oxide semiconductors, Complementary |x Defects. | |
| 650 | 0 | |a Metal oxide semiconductors, Complementary |x Reliability. | |
| 650 | 6 | |a MOS complémentaires |x Défauts. | |
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| 650 | 7 | |a Metal oxide semiconductors, Complementary |x Reliability |2 fast | |
| 655 | 0 | |a Electronic books. | |
| 700 | 1 | |a Hsu, Sheng-Fu. | |
| 758 | |i has work: |a Transient-induced latchup in CMOS integrated circuits (Text) |1 https://id.oclc.org/worldcat/entity/E39PCG6rBpmrgYf63PHrDJq6Dq |4 https://id.oclc.org/worldcat/ontology/hasWork | ||
| 776 | 0 | 8 | |i Print version: |a Ker, Ming-Dou. |t Transient-induced latchup in CMOS integrated circuits. |d Singapore ; Hoboken, NJ : Wiley ; [Piscataway, NJ] : IEEE Press, ©2009 |z 9780470824078 |w (DLC) 2008045600 |w (OCoLC)264669592 |
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