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Transient-induced latchup in CMOS integrated circuits /
"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the c...
| Cote: | Libro Electrónico |
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| Autres auteurs: | |
| Format: | Électronique eBook |
| Langue: | Inglés |
| Publié: |
[Piscataway, NJ] : Singapore ; Hoboken, NJ :
IEEE Press ; John Wiley & Sons (Asia),
©2009.
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| Sujets: | |
| Accès en ligne: | Texto completo |
| Résumé: | "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description. |
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| Description matérielle: | 1 online resource (xiii, 249 pages) : illustrations |
| Bibliographie: | Includes bibliographical references and index. |
| ISBN: | 9780470824085 0470824085 9780470824092 0470824093 1282382187 9781282382183 |