Cryptographic Hardware and Embedded Systems -- CHES 2010 12th International Workshop, Santa Barbara, USA, August 17-20,2010, Proceedings /

Detalles Bibliográficos
Clasificación:Libro Electrónico
Autor Corporativo: SpringerLink (Online service)
Otros Autores: Mangard, Stefan (Editor ), Standaert, Francois-Xavier (Editor )
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Berlin, Heidelberg : Springer Berlin Heidelberg : Imprint: Springer, 2010.
Edición:1st ed. 2010.
Colección:Security and Cryptology ; 6225
Temas:
Cryptography.
Data encryption (Computer science).
Coding theory.
Information theory.
Data structures (Computer science).
Data protection.
Algorithms.
Computer science-Mathematics.
Discrete mathematics.
Cryptology.
Coding and Information Theory.
Data Structures and Information Theory.
Data and Information Security.
Discrete Mathematics in Computer Science.
Acceso en línea:Texto Completo
Tabla de Contenidos:
  • Low Cost Cryptography
  • Quark: A Lightweight Hash
  • PRINTcipher: A Block Cipher for IC-Printing
  • Sponge-Based Pseudo-Random Number Generators
  • Efficient Implementations I
  • A High Speed Coprocessor for Elliptic Curve Scalar Multiplications over
  • Co-Z Addition Formulæ and Binary Ladders on Elliptic Curves
  • Efficient Techniques for High-Speed Elliptic Curve Cryptography
  • Side-Channel Attacks and Countermeasures I
  • Analysis and Improvement of the Random Delay Countermeasure of CHES 2009
  • New Results on Instruction Cache Attacks
  • Correlation-Enhanced Power Analysis Collision Attack
  • Side-Channel Analysis of Six SHA-3 Candidates
  • Tamper Resistance and Hardware Trojans
  • Flash Memory 'Bumping' Attacks
  • Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection
  • When Failure Analysis Meets Side-Channel Attacks
  • Efficient Implementations II
  • Fast Exhaustive Search for Polynomial Systems in
  • 256 Bit Standardized Crypto for 650 GE - GOST Revisited
  • Mixed Bases for Efficient Inversion in and Conversion Matrices of SubBytes of AES
  • SHA-3
  • Developing a Hardware Evaluation Method for SHA-3 Candidates
  • Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs
  • Performance Analysis of the SHA-3 Candidates on Exotic Multi-core Architectures
  • XBX: eXternal Benchmarking eXtension for the SUPERCOP Crypto Benchmarking Framework
  • Fault Attacks and Countermeasures
  • Public Key Perturbation of Randomized RSA Implementations
  • Fault Sensitivity Analysis
  • PUFs and RNGs
  • An Alternative to Error Correction for SRAM-Like PUFs
  • New High Entropy Element for FPGA Based True Random Number Generators
  • The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes
  • New Designs
  • Garbled Circuits for Leakage-Resilience: Hardware Implementation and Evaluation of One-Time Programs
  • ARMADILLO: A Multi-purpose Cryptographic Primitive Dedicated to Hardware
  • Side-Channel Attacks and Countermeasures II
  • Provably Secure Higher-Order Masking of AES
  • Algebraic Side-Channel Analysis in the Presence of Errors
  • Coordinate Blinding over Large Prime Fields.

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