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Embedded Computer Systems: Architectures, Modeling, and Simulation 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings /
This book constitutes the refereed proceedings of the 9th International Workshop on Architectures, Modeling, and Simulation, SAMOS 2009, held on Samos, Greece, on July 20-23, 2009. The 18 regular papers presented were carefully reviewed and selected from 52 submissions. The papers are organized in t...
| Clasificación: | Libro Electrónico |
|---|---|
| Autor Corporativo: | |
| Otros Autores: | , , , |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
Berlin, Heidelberg :
Springer Berlin Heidelberg : Imprint: Springer,
2009.
|
| Edición: | 1st ed. 2009. |
| Colección: | Theoretical Computer Science and General Issues,
5657 |
| Temas: | |
| Acceso en línea: | Texto Completo |
MARC
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| 245 | 1 | 0 | |a Embedded Computer Systems: Architectures, Modeling, and Simulation |h [electronic resource] : |b 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009, Proceedings / |c edited by Koen Bertels, Nikitas Dimopoulos, Cristina Silvano, Stephan Wong. |
| 250 | |a 1st ed. 2009. | ||
| 264 | 1 | |a Berlin, Heidelberg : |b Springer Berlin Heidelberg : |b Imprint: Springer, |c 2009. | |
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| 490 | 1 | |a Theoretical Computer Science and General Issues, |x 2512-2029 ; |v 5657 | |
| 505 | 0 | |a Beachnote -- What Else Is Broken? Can We Fix It? -- Architectures for Multimedia -- Programmable and Scalable Architecture for Graphics Processing Units -- The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors -- CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey -- Programmable Accelerators for Reconfigurable Video Decoder -- Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study -- Multiple Description Scalable Coding for Video Transmission over Unreliable Networks -- Multi/Many Cores Architectures -- Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC -- Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture -- Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management -- A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA -- VLSI Architectures Design -- Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing -- Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata -- Prediction in Dynamic SDRAM Controller Policies -- Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI -- Architecture Modeling and Exploration Tools -- Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration -- Modeling Scalable SIMD DSPs in LISA -- NoGAP: A Micro Architecture Construction Framework -- A Comparison of NoTA and GENESYS -- Special Session 1: Instruction-Set Customization -- to Instruction-Set Customization -- Constraint-Driven Identification of Application Specific Instructions in the DURASE System -- A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) -- Runtime Adaptive Extensible Embedded Processors - A Survey -- Special Session 2: The Future of Reconfigurable Computing and Processor Architectures -- to the Future of Reconfigurable Computing and Processor Architectures -- An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems -- Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study -- Reconfigurable Multicore Server Processors for Low Power Operation -- Reconfigurable Computing in the New Age of Parallelism -- Reconfigurable Multithreading Architectures: A Survey -- Special Session 3: Mastering Cell BE and GPU Execution Platforms -- to Mastering Cell BE and GPU Execution Platforms -- Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors -- Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs -- Experiences with Cell-BE and GPU for Tomography -- Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell -- Exploiting Locality on the Cell/B.E. through Bypassing -- Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System. | |
| 520 | |a This book constitutes the refereed proceedings of the 9th International Workshop on Architectures, Modeling, and Simulation, SAMOS 2009, held on Samos, Greece, on July 20-23, 2009. The 18 regular papers presented were carefully reviewed and selected from 52 submissions. The papers are organized in topical sections on architectures for multimedia, multi/many cores architectures, VLSI architectures design, architecture modeling and exploration tools. In addition there are 14 papers from three special sessions which were organized on topics of current interest: instruction-set customization, reconfigurable computing and processor architectures, and mastering cell BE and GPU execution platforms. | ||
| 650 | 0 | |a Computer systems. | |
| 650 | 0 | |a Computers. | |
| 650 | 0 | |a Microprocessors. | |
| 650 | 0 | |a Computer architecture. | |
| 650 | 0 | |a Computer networks . | |
| 650 | 0 | |a Electronic digital computers |x Evaluation. | |
| 650 | 1 | 4 | |a Computer System Implementation. |
| 650 | 2 | 4 | |a Computer Hardware. |
| 650 | 2 | 4 | |a Processor Architectures. |
| 650 | 2 | 4 | |a Computer Communication Networks. |
| 650 | 2 | 4 | |a System Performance and Evaluation. |
| 700 | 1 | |a Bertels, Koen. |e editor. |0 (orcid)0000-0001-9310-4885 |1 https://orcid.org/0000-0001-9310-4885 |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Dimopoulos, Nikitas. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Silvano, Cristina. |e editor. |0 (orcid)0000-0003-1668-0883 |1 https://orcid.org/0000-0003-1668-0883 |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
| 700 | 1 | |a Wong, Stephan. |e editor. |4 edt |4 http://id.loc.gov/vocabulary/relators/edt | |
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| 773 | 0 | |t Springer Nature eBook | |
| 776 | 0 | 8 | |i Printed edition: |z 9783642031397 |
| 776 | 0 | 8 | |i Printed edition: |z 9783642031373 |
| 830 | 0 | |a Theoretical Computer Science and General Issues, |x 2512-2029 ; |v 5657 | |
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