A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof /

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The...

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Bibliographic Details
Call Number:Libro Electrónico
Main Authors: Kovalev, Mikhail (Author), Müller, Silvia M. (Author), Paul, Wolfgang J. (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:Inglés
Published: Cham : Springer International Publishing : Imprint: Springer, 2014.
Edition:1st ed. 2014.
Series:Theoretical Computer Science and General Issues, 9000
Subjects:
Algorithms.
Software engineering.
Computers.
Microprocessors.
Computer architecture.
Computer networks .
Compilers (Computer programs).
Software Engineering.
Computer Hardware.
Processor Architectures.
Computer Communication Networks.
Compilers and Interpreters.
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