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Clock Generators for SOC Processors Circuits and Architectures /

Current literature is filled with textbooks and research papers describing frequency synthesizers from a front-end wireless transceiver perspective. The emphasis has historically been on evaluating the frequency synthesizer's performance in the frequency domain, i.e. in terms of phase noise and...

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Bibliographic Details
Call Number:Libro Electrónico
Main Author: Fahim, Amr (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:Inglés
Published: New York, NY : Springer US : Imprint: Springer, 2005.
Edition:1st ed. 2005.
Subjects:
Online Access:Texto Completo
Table of Contents:
  • Phase-Locked Loop Fundamentals
  • Low-Voltage Analog Cmos Design
  • Jitter Analysis in Phase-Locked Loops
  • Low-Jitter PLL Architectures
  • Digital PLL Design
  • DSP Clock Generator Architectures
  • Design for Testability in PLLs
  • Clock Partitioning and Skew Control.