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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptabl...
| Clasificación: | Libro Electrónico |
|---|---|
| Autores principales: | , |
| Autor Corporativo: | |
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
New York, NY :
Springer US : Imprint: Springer,
2007.
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| Edición: | 2nd ed. 2007. |
| Colección: | Frontiers in Electronic Testing ;
34 |
| Temas: | |
| Acceso en línea: | Texto Completo |
Tabla de Contenidos:
- Functional and Parametric Defect Models
- Digital CMOS Fault Modeling
- Defects in Logic Circuits and their Test Implications
- Testing Defects and Parametric Variations in RAMs
- Defect-Oriented Analog Testing
- Yield Engineering
- Conclusion.