Functional Verification of Programmable Embedded Architectures A Top-Down Approach /

Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many ex...

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Bibliographic Details
Call Number:Libro Electrónico
Main Authors: Mishra, Prabhat (Author), Dutt, Nikil D. (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:Inglés
Published: New York, NY : Springer US : Imprint: Springer, 2005.
Edition:1st ed. 2005.
Subjects:
Electronic circuits.
Microprocessors.
Computer architecture.
Computers, Special purpose.
Computer-aided engineering.
Electronic digital computers-Evaluation.
Electrical engineering.
Electronic Circuits and Systems.
Processor Architectures.
Special Purpose and Application-Based Systems.
Computer-Aided Engineering (CAD, CAE) and Design.
System Performance and Evaluation.
Electrical and Electronic Engineering.
Online Access:Texto Completo
Table of Contents:
  • to Functional Verification
  • Architecture Specification
  • Architecture Specification
  • Validation of Specification
  • Top-Down Validation
  • Executable Model Generation
  • Design Validation
  • Functional Test Generation
  • Future Directions
  • Conclusions.

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