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Functional Verification of Programmable Embedded Architectures A Top-Down Approach /
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many ex...
| Call Number: | Libro Electrónico |
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| Main Authors: | , |
| Corporate Author: | |
| Format: | Electronic eBook |
| Language: | Inglés |
| Published: |
New York, NY :
Springer US : Imprint: Springer,
2005.
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| Edition: | 1st ed. 2005. |
| Subjects: | |
| Online Access: | Texto Completo |