Cargando…
Practical Digital Design : An Introduction to VHDL /
CHAPTER 7 SEQUENTIAL STATEMENTS -- Null Statement -- Wait Statement -- If Statement -- Case Statement -- Loop Statement -- Loop Control Statements -- Assertion and Report Statements -- Signal Assignment -- Variable Assignment -- Summary -- CHAPTER 8 THE PROCESS STATEMENT -- Process Review -- Combina...
| Autor principal: | |
|---|---|
| Formato: | Electrónico eBook |
| Idioma: | Inglés |
| Publicado: |
West Lafayette, IN :
Purdue University Press,
[2022]
|
| Colección: | Book collections on Project MUSE.
|
| Temas: | |
| Acceso en línea: | Texto completo |
MARC
| LEADER | 00000cam a22000004a 4500 | ||
|---|---|---|---|
| 001 | musev2_97899 | ||
| 003 | MdBmJHUP | ||
| 005 | 20230905053259.0 | ||
| 006 | m o d | ||
| 007 | cr||||||||nn|n | ||
| 008 | 220510s2022 inu o 00 0 eng d | ||
| 020 | |a 9781612497679 | ||
| 020 | |z 9781612497662 | ||
| 035 | |a (OCoLC)1315643039 | ||
| 040 | |a MdBmJHUP |c MdBmJHUP | ||
| 100 | 1 | |a Reidenbach, Bruce, |e author. | |
| 245 | 1 | 0 | |a Practical Digital Design : |b An Introduction to VHDL / |c Bruce Reidenbach. |
| 264 | 1 | |a West Lafayette, IN : |b Purdue University Press, |c [2022] | |
| 264 | 3 | |a Baltimore, Md. : |b Project MUSE, |c 2022 | |
| 264 | 4 | |c ©[2022] | |
| 300 | |a 1 online resource (440 pages). | ||
| 336 | |a text |b txt |2 rdacontent | ||
| 337 | |a computer |b c |2 rdamedia | ||
| 338 | |a online resource |b cr |2 rdacarrier | ||
| 505 | 0 | |a Cover -- PRACTICAL DIGITAL DESIGN -- Title -- Copyright -- Dedication -- TABLE OF CONTENTS -- PREFACE -- ACKNOWLEDGMENTS -- ABOUT THE AUTHOR -- CHAPTER 1 INTRODUCTION -- Target Audience -- A Brief History of Digital Design -- The Need for a Hardware Description Language -- A Brief Tour of a VHDL Model -- CHAPTER 2 SIGNALS, TIME, AND THE SIMULATION CYCLE -- Signals -- Events -- Drivers -- Delta Time -- The Simulation Cycle -- CHAPTER 3 THE VHDL DESIGN ENVIRONMENT -- Modeling Styles -- Design Flow -- Data Types -- Type Definition -- Vector Data Types -- Operators and Precedence | |
| 505 | 0 | |a Design Libraries -- Predefined Packages -- STANDARD Package -- STD_LOGIC_1164 Package -- NUMERIC_STD Package -- TEXTIO Package -- Type Conversion -- Type Qualification -- Attributes -- VHDL Language Versions -- Coding Style -- Vertical Alignment -- VHDL Identifier Naming Rules -- Comments -- CHAPTER 4 DECLARATIONS -- Syntax Notation -- Object Declaration Syntax -- Custom Type Declarations -- Integer Types -- Floating Point Types -- Enumerated Types -- Array Types -- Record Types -- Physical Types -- Access Types -- Alias Declarations -- CHAPTER 5 LIBRARIES AND DESIGN UNITS -- Library Units | |
| 505 | 0 | |a Entity Declaration -- Ports -- Generics -- Architecture Declaration -- Package Declaration -- Package Body Declaration -- Configuration Declaration -- Design Units -- Context Clause -- Summary -- CHAPTER 6 CONCURRENT STATEMENTS -- Conditional Signal Assignment Statement -- Selected Signal Assignment Statement -- Waveform Specification -- Delay Models -- Generate Statement -- Component Instantiation -- Concurrent Assertion Statement -- Component Declaration -- Configuration Specification -- Component Instantiation Statement -- Direct Entity Instantiation -- Block Statement -- Process Statement | |
| 505 | 0 | |a Behavioral Model -- Synthesizable Model -- Structural Model -- Summary -- Engine Management System -- CHAPTER 10 SUBPROGRAMS -- Functions -- Return Statements -- Examples -- Overloading -- Pure versus Impure Functions -- Procedures -- Return Statements -- Parameter Passing Details -- Signal Parameters -- Concurrent Procedure Calls -- Procedures as Functions -- Summary -- CHAPTER 11 SIMULATION AND TEST BENCHES -- Simulation -- Simulation Phases -- Test Benches -- Test Bench Control -- Races -- Input Drivers -- Output Monitors -- Test Bench Example -- Test Bench Types -- Directed Testing | |
| 520 | |a CHAPTER 7 SEQUENTIAL STATEMENTS -- Null Statement -- Wait Statement -- If Statement -- Case Statement -- Loop Statement -- Loop Control Statements -- Assertion and Report Statements -- Signal Assignment -- Variable Assignment -- Summary -- CHAPTER 8 THE PROCESS STATEMENT -- Process Review -- Combinatorial Logic -- Level Sensitive Latches -- Clocked Logic -- Process Examples -- Register Files -- Shift Registers -- Adders -- Counters -- State Machines -- Memory Arrays -- Process Construction Guidelines -- Summary -- CHAPTER 9 MODELING CASE STUDIES -- Modeling Style -- Binary Adder. | ||
| 588 | |a Description based on print version record. | ||
| 650 | 7 | |a COMPUTERS / Computer Engineering |2 bisacsh | |
| 650 | 7 | |a VHDL (Computer hardware description language) |2 fast |0 (OCoLC)fst01163476 | |
| 650 | 0 | |a VHDL (Computer hardware description language) | |
| 655 | 7 | |a Electronic books. |2 local | |
| 710 | 2 | |a Project Muse. |e distributor | |
| 830 | 0 | |a Book collections on Project MUSE. | |
| 856 | 4 | 0 | |z Texto completo |u https://projectmuse.uam.elogim.com/book/97899/ |
| 945 | |a Project MUSE - Custom Collection | ||
| 945 | |a Project MUSE - 2022 Complete | ||
| 945 | |a Project MUSE - 2022 Science, Technology and Media | ||