Formal verification : an essential toolkit for modern VLSI design /

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Formal Verification: An Essential Toolkit for Modern VLSI Design, Second Edition presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mat...

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Detalles Bibliográficos
Clasificación:Libro Electrónico
Autores principales: Seligman, Erik (Autor), Schubert, E. Thomas, 1959- (Autor), Kumar, M. V. Achutha Kiran (Autor)
Formato: Electrónico eBook
Idioma:Inglés
Publicado: Cambridge, MA : Morgan Kaufmann, [2023]
Edición:Second edition.
Temas:
Electronic circuits > Testing.
Integrated circuits > Very large scale integration > Design and construction.
Verilog (Computer hardware description language)
Verilog (Langage de description de mat�eriel informatique)
Electronic circuits > Testing
Integrated circuits > Very large scale integration > Design and construction
Acceso en línea:Texto completo
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Formal verification : an essential toolkit for modern VLSI design /
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Electrónico eBook
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Formal verification : an essential toolkit for modern VLSI design /
Texto completo (Requiere registro previo con correo institucional)
Electrónico eBook
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Formal verification : an essential toolkit for modern VLSI design /
por Seligman, Erik
Publicado 2015
Texto completo
Electrónico eBook
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